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-rw-r--r--lib/Target/ARM/ARMRegisterInfo.td4
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td
index 962158580c..99418733c3 100644
--- a/lib/Target/ARM/ARMRegisterInfo.td
+++ b/lib/Target/ARM/ARMRegisterInfo.td
@@ -540,4 +540,6 @@ def QQQQPR : RegisterClass<"ARM", [v8i64],
}
// Condition code registers.
-def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
+def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]> {
+ let isAllocatable = 0;
+}