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-rw-r--r--lib/Target/PowerPC/PPCScheduleA2.td104
1 files changed, 52 insertions, 52 deletions
diff --git a/lib/Target/PowerPC/PPCScheduleA2.td b/lib/Target/PowerPC/PPCScheduleA2.td
index 509de816aa..bd95924be8 100644
--- a/lib/Target/PowerPC/PPCScheduleA2.td
+++ b/lib/Target/PowerPC/PPCScheduleA2.td
@@ -26,117 +26,117 @@ def A2_FU : FuncUnit; // FI pipeline
def PPCA2Itineraries : ProcessorItineraries<
[A2_XU, A2_FU], [], [
InstrItinData<IIC_IntSimple, [InstrStage<1, [A2_XU]>],
- [1, 1, 1]>,
+ [1, 0, 0]>,
InstrItinData<IIC_IntGeneral, [InstrStage<1, [A2_XU]>],
- [2, 1, 1]>,
+ [2, 0, 0]>,
InstrItinData<IIC_IntCompare, [InstrStage<1, [A2_XU]>],
- [2, 1, 1]>,
+ [2, 0, 0]>,
InstrItinData<IIC_IntDivW, [InstrStage<1, [A2_XU]>],
- [39, 1, 1]>,
+ [39, 0, 0]>,
InstrItinData<IIC_IntDivD, [InstrStage<1, [A2_XU]>],
- [71, 1, 1]>,
+ [71, 0, 0]>,
InstrItinData<IIC_IntMulHW, [InstrStage<1, [A2_XU]>],
- [5, 1, 1]>,
+ [5, 0, 0]>,
InstrItinData<IIC_IntMulHWU, [InstrStage<1, [A2_XU]>],
- [5, 1, 1]>,
+ [5, 0, 0]>,
InstrItinData<IIC_IntMulLI, [InstrStage<1, [A2_XU]>],
- [6, 1, 1]>,
+ [6, 0, 0]>,
InstrItinData<IIC_IntRotate, [InstrStage<1, [A2_XU]>],
- [2, 1, 1]>,
+ [2, 0, 0]>,
InstrItinData<IIC_IntRotateD, [InstrStage<1, [A2_XU]>],
- [2, 1, 1]>,
+ [2, 0, 0]>,
InstrItinData<IIC_IntRotateDI, [InstrStage<1, [A2_XU]>],
- [2, 1, 1]>,
+ [2, 0, 0]>,
InstrItinData<IIC_IntShift, [InstrStage<1, [A2_XU]>],
- [2, 1, 1]>,
+ [2, 0, 0]>,
InstrItinData<IIC_IntTrapW, [InstrStage<1, [A2_XU]>],
- [2, 1]>,
+ [2, 0]>,
InstrItinData<IIC_IntTrapD, [InstrStage<1, [A2_XU]>],
- [2, 1]>,
+ [2, 0]>,
InstrItinData<IIC_BrB, [InstrStage<1, [A2_XU]>],
- [6, 1, 1]>,
+ [6, 0, 0]>,
InstrItinData<IIC_BrCR, [InstrStage<1, [A2_XU]>],
- [1, 1, 1]>,
+ [1, 0, 0]>,
InstrItinData<IIC_BrMCR, [InstrStage<1, [A2_XU]>],
- [5, 1, 1]>,
+ [5, 0, 0]>,
InstrItinData<IIC_BrMCRX, [InstrStage<1, [A2_XU]>],
- [1, 1, 1]>,
+ [1, 0, 0]>,
InstrItinData<IIC_LdStDCBA, [InstrStage<1, [A2_XU]>],
- [1, 1, 1]>,
+ [1, 0, 0]>,
InstrItinData<IIC_LdStDCBF, [InstrStage<1, [A2_XU]>],
- [1, 1, 1]>,
+ [1, 0, 0]>,
InstrItinData<IIC_LdStDCBI, [InstrStage<1, [A2_XU]>],
- [1, 1, 1]>,
+ [1, 0, 0]>,
InstrItinData<IIC_LdStLoad, [InstrStage<1, [A2_XU]>],
- [6, 1, 1]>,
+ [6, 0, 0]>,
InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [A2_XU]>],
- [6, 8, 1, 1]>,
+ [6, 8, 0, 0]>,
InstrItinData<IIC_LdStLDU, [InstrStage<1, [A2_XU]>],
- [6, 1, 1]>,
+ [6, 0, 0]>,
InstrItinData<IIC_LdStStore, [InstrStage<1, [A2_XU]>],
- [1, 1, 1]>,
+ [0, 0, 0]>,
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [A2_XU]>],
- [2, 1, 1, 1]>,
+ [2, 0, 0, 0]>,
InstrItinData<IIC_LdStICBI, [InstrStage<1, [A2_XU]>],
- [16, 1, 1]>,
+ [16, 0, 0]>,
InstrItinData<IIC_LdStSTFD, [InstrStage<1, [A2_XU]>],
- [1, 1, 1]>,
+ [0, 0, 0]>,
InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [A2_XU]>],
- [2, 1, 1, 1]>,
+ [2, 0, 0, 0]>,
InstrItinData<IIC_LdStLFD, [InstrStage<1, [A2_XU]>],
- [7, 1, 1]>,
+ [7, 0, 0]>,
InstrItinData<IIC_LdStLFDU, [InstrStage<1, [A2_XU]>],
- [7, 9, 1, 1]>,
+ [7, 9, 0, 0]>,
InstrItinData<IIC_LdStLHA, [InstrStage<1, [A2_XU]>],
- [6, 1, 1]>,
+ [6, 0, 0]>,
InstrItinData<IIC_LdStLHAU, [InstrStage<1, [A2_XU]>],
- [6, 8, 1, 1]>,
+ [6, 8, 0, 0]>,
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [A2_XU]>],
- [82, 1, 1]>, // L2 latency
+ [82, 0, 0]>, // L2 latency
InstrItinData<IIC_LdStSTD, [InstrStage<1, [A2_XU]>],
- [1, 1, 1]>,
+ [0, 0, 0]>,
InstrItinData<IIC_LdStSTDU, [InstrStage<1, [A2_XU]>],
- [2, 1, 1, 1]>,
+ [2, 0, 0, 0]>,
InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [A2_XU]>],
- [82, 1, 1]>, // L2 latency
+ [82, 0, 0]>, // L2 latency
InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [A2_XU]>],
- [82, 1, 1]>, // L2 latency
+ [82, 0, 0]>, // L2 latency
InstrItinData<IIC_LdStSync, [InstrStage<1, [A2_XU]>],
[6]>,
InstrItinData<IIC_SprISYNC, [InstrStage<1, [A2_XU]>],
[16]>,
InstrItinData<IIC_SprMTMSR, [InstrStage<1, [A2_XU]>],
- [16, 1]>,
+ [16, 0]>,
InstrItinData<IIC_SprMFCR, [InstrStage<1, [A2_XU]>],
- [6, 1]>,
+ [6, 0]>,
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [A2_XU]>],
- [4, 1]>,
+ [4, 0]>,
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [A2_XU]>],
- [6, 1]>,
+ [6, 0]>,
InstrItinData<IIC_SprMFTB, [InstrStage<1, [A2_XU]>],
- [4, 1]>,
+ [4, 0]>,
InstrItinData<IIC_SprMTSPR, [InstrStage<1, [A2_XU]>],
- [6, 1]>,
+ [6, 0]>,
InstrItinData<IIC_SprRFI, [InstrStage<1, [A2_XU]>],
[16]>,
InstrItinData<IIC_SprSC, [InstrStage<1, [A2_XU]>],
[16]>,
InstrItinData<IIC_FPGeneral, [InstrStage<1, [A2_FU]>],
- [6, 1, 1]>,
+ [6, 0, 0]>,
InstrItinData<IIC_FPAddSub, [InstrStage<1, [A2_FU]>],
- [6, 1, 1]>,
+ [6, 0, 0]>,
InstrItinData<IIC_FPCompare, [InstrStage<1, [A2_FU]>],
- [5, 1, 1]>,
+ [5, 0, 0]>,
InstrItinData<IIC_FPDivD, [InstrStage<1, [A2_FU]>],
- [72, 1, 1]>,
+ [72, 0, 0]>,
InstrItinData<IIC_FPDivS, [InstrStage<1, [A2_FU]>],
- [59, 1, 1]>,
+ [59, 0, 0]>,
InstrItinData<IIC_FPSqrt, [InstrStage<1, [A2_FU]>],
- [69, 1, 1]>,
+ [69, 0, 0]>,
InstrItinData<IIC_FPFused, [InstrStage<1, [A2_FU]>],
- [6, 1, 1, 1]>,
+ [6, 0, 0, 0]>,
InstrItinData<IIC_FPRes, [InstrStage<1, [A2_FU]>],
- [6, 1]>
+ [6, 0]>
]>;
// ===---------------------------------------------------------------------===//
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 17:47:59 +0000