diff options
Diffstat (limited to 'lib/Target/X86')
| -rw-r--r-- | lib/Target/X86/Disassembler/X86DisassemblerDecoder.h | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86FastISel.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86Schedule.td | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h index c4c86ada3f..ac3b39df54 100644 --- a/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h +++ b/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h @@ -563,7 +563,7 @@ struct InternalInstruction { uint8_t prefixPresent[0x100]; /* contains the location (for use with the reader) of the prefix byte */ uint64_t prefixLocations[0x100]; - /* The value of the vector extention prefix(EVEX/VEX/XOP), if present */ + /* The value of the vector extension prefix(EVEX/VEX/XOP), if present */ uint8_t vectorExtensionPrefix[4]; /* The type of the vector extension prefix */ VectorExtensionType vectorExtensionType; diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index 9fdc58a311..d653c871b2 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -1512,7 +1512,7 @@ bool X86FastISel::X86SelectSelect(const Instruction *I) { // garbage. Indeed, only the less significant bit is supposed to be accurate. // If we read more than the lsb, we may see non-zero values whereas lsb // is zero. Therefore, we have to truncate Op0Reg to i1 for the select. - // This is acheived by performing TEST against 1. + // This is achieved by performing TEST against 1. BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8ri)) .addReg(Op0Reg).addImm(1); unsigned ResultReg = createResultReg(RC); diff --git a/lib/Target/X86/X86Schedule.td b/lib/Target/X86/X86Schedule.td index 0556437b83..ac28d1e543 100644 --- a/lib/Target/X86/X86Schedule.td +++ b/lib/Target/X86/X86Schedule.td @@ -577,7 +577,7 @@ def IIC_NOP : InstrItinClass; //===----------------------------------------------------------------------===// // Processor instruction itineraries. -// IssueWidth is analagous to the number of decode units. Core and its +// IssueWidth is analogous to the number of decode units. Core and its // descendents, including Nehalem and SandyBridge have 4 decoders. // Resources beyond the decoder operate on micro-ops and are bufferred // so adjacent micro-ops don't directly compete. |