diff options
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/ARMFastISel.cpp | 12 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 3 |
2 files changed, 5 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 7527c8496d..6611862ca0 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -1028,8 +1028,7 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, RC = &ARM::GPRRegClass; break; case MVT::i16: - if (Alignment && Alignment < 2 && (!Subtarget->allowsUnalignedMem() || - TM.Options.StrictAlign)) + if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem()) return false; if (isThumb2) { @@ -1044,8 +1043,7 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, RC = &ARM::GPRRegClass; break; case MVT::i32: - if (Alignment && Alignment < 4 && (!Subtarget->allowsUnalignedMem() || - TM.Options.StrictAlign)) + if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem()) return false; if (isThumb2) { @@ -1154,8 +1152,7 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, } break; case MVT::i16: - if (Alignment && Alignment < 2 && (!Subtarget->allowsUnalignedMem() || - TM.Options.StrictAlign)) + if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem()) return false; if (isThumb2) { @@ -1169,8 +1166,7 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, } break; case MVT::i32: - if (Alignment && Alignment < 4 && (!Subtarget->allowsUnalignedMem() || - TM.Options.StrictAlign)) + if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem()) return false; if (isThumb2) { diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 65cc49e1c3..3b9558bc2a 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -9119,8 +9119,7 @@ bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc, bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus - bool AllowsUnaligned = Subtarget->allowsUnalignedMem() && - !getTargetMachine().Options.StrictAlign; + bool AllowsUnaligned = Subtarget->allowsUnalignedMem(); switch (VT.getSimpleVT().SimpleTy) { default: |