diff options
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/BranchFolding.cpp | 2 | ||||
-rw-r--r-- | lib/CodeGen/PostRASchedulerList.cpp | 4 | ||||
-rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 5 | ||||
-rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.h | 2 | ||||
-rw-r--r-- | lib/Target/CellSPU/SPURegisterInfo.h | 5 | ||||
-rw-r--r-- | lib/Target/Hexagon/HexagonRegisterInfo.h | 4 | ||||
-rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.cpp | 5 | ||||
-rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.h | 2 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 6 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.h | 2 | ||||
-rw-r--r-- | lib/Target/X86/X86RegisterInfo.cpp | 6 | ||||
-rw-r--r-- | lib/Target/X86/X86RegisterInfo.h | 3 | ||||
-rw-r--r-- | lib/Target/X86/X86Subtarget.cpp | 4 | ||||
-rw-r--r-- | lib/Target/X86/X86Subtarget.h | 2 | ||||
-rw-r--r-- | lib/Target/XCore/XCoreRegisterInfo.cpp | 5 | ||||
-rw-r--r-- | lib/Target/XCore/XCoreRegisterInfo.h | 2 |
16 files changed, 54 insertions, 5 deletions
diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp index ef1d2baed9..c7f2d64a36 100644 --- a/lib/CodeGen/BranchFolding.cpp +++ b/lib/CodeGen/BranchFolding.cpp @@ -188,7 +188,7 @@ bool BranchFolder::OptimizeFunction(MachineFunction &MF, // Use a RegScavenger to help update liveness when required. MachineRegisterInfo &MRI = MF.getRegInfo(); - if (MRI.tracksLiveness() && TRI->requiresRegisterScavenging(MF)) + if (MRI.tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF)) RS = new RegScavenger(); else MRI.invalidateLiveness(); diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index 24d3e5ab0c..13feaec7d8 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -206,6 +206,10 @@ SchedulePostRATDList::SchedulePostRATDList( const InstrItineraryData *InstrItins = TM.getInstrItineraryData(); HazardRec = TM.getInstrInfo()->CreateTargetPostRAHazardRecognizer(InstrItins, this); + + assert((AntiDepMode == TargetSubtargetInfo::ANTIDEP_NONE || + MRI.tracksLiveness()) && + "Live-ins must be accurate for anti-dependency breaking"); AntiDepBreak = ((AntiDepMode == TargetSubtargetInfo::ANTIDEP_ALL) ? (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) : diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 2a09b20b9c..9442e4bb71 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -712,6 +712,11 @@ requiresRegisterScavenging(const MachineFunction &MF) const { } bool ARMBaseRegisterInfo:: +trackLivenessAfterRegAlloc(const MachineFunction &MF) const { + return true; +} + +bool ARMBaseRegisterInfo:: requiresFrameIndexScavenging(const MachineFunction &MF) const { return true; } diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.h b/lib/Target/ARM/ARMBaseRegisterInfo.h index af7935147e..4eeee70cac 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.h +++ b/lib/Target/ARM/ARMBaseRegisterInfo.h @@ -173,6 +173,8 @@ public: virtual bool requiresRegisterScavenging(const MachineFunction &MF) const; + virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const; + virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const; virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const; diff --git a/lib/Target/CellSPU/SPURegisterInfo.h b/lib/Target/CellSPU/SPURegisterInfo.h index e5ab224225..9fae8f2947 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.h +++ b/lib/Target/CellSPU/SPURegisterInfo.h @@ -63,6 +63,11 @@ namespace llvm { virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { return true; } + //! Enable tracking of liveness after register allocation, since register + // scavenging is enabled. + virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const + { return true; } + //! Return the reserved registers BitVector getReservedRegs(const MachineFunction &MF) const; diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.h b/lib/Target/Hexagon/HexagonRegisterInfo.h index 6cf727bc02..85355ae7be 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.h +++ b/lib/Target/Hexagon/HexagonRegisterInfo.h @@ -73,6 +73,10 @@ struct HexagonRegisterInfo : public HexagonGenRegisterInfo { return true; } + bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { + return true; + } + // Debug information queries. unsigned getRARegister() const; unsigned getFrameRegister(const MachineFunction &MF) const; diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index 67f2834ab6..952666301a 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -136,6 +136,11 @@ MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { return true; } +bool +MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { + return true; +} + // This function eliminate ADJCALLSTACKDOWN, // ADJCALLSTACKUP pseudo instructions void MipsRegisterInfo:: diff --git a/lib/Target/Mips/MipsRegisterInfo.h b/lib/Target/Mips/MipsRegisterInfo.h index 0716d29b2f..6d3f83f506 100644 --- a/lib/Target/Mips/MipsRegisterInfo.h +++ b/lib/Target/Mips/MipsRegisterInfo.h @@ -49,6 +49,8 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo { virtual bool requiresRegisterScavenging(const MachineFunction &MF) const; + virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const; + void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index ef1357137d..41e724ffa9 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -89,6 +89,12 @@ PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32; } +bool +PPCRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { + return requiresRegisterScavenging(MF); +} + + /// getPointerRegClass - Return the register class to use to hold pointers. /// This is used for addressing modes. const TargetRegisterClass * diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h index b1e6a7218e..775c3f1311 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/lib/Target/PowerPC/PPCRegisterInfo.h @@ -50,6 +50,8 @@ public: /// FIXME (64-bit): Should be inlined. bool requiresRegisterScavenging(const MachineFunction &MF) const; + bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const; + void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const; diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index e612f496da..6e00a552b6 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -90,6 +90,12 @@ int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const { return -1; } +bool +X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { + // Only enable when post-RA scheduling is enabled and this is needed. + return TM.getSubtargetImpl()->postRAScheduler(); +} + int X86RegisterInfo::getSEHRegNum(unsigned i) const { int reg = X86_MC::getX86RegNum(i); diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h index bee03936f1..4809fd5c11 100644 --- a/lib/Target/X86/X86RegisterInfo.h +++ b/lib/Target/X86/X86RegisterInfo.h @@ -65,7 +65,8 @@ public: int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const; /// Code Generation virtual methods... - /// + /// + virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const; /// getMatchingSuperRegClass - Return a subclass of the specified register /// class A so that each register in it has a sub-register of the diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp index ed1a40965a..452dd7eba3 100644 --- a/lib/Target/X86/X86Subtarget.cpp +++ b/lib/Target/X86/X86Subtarget.cpp @@ -424,9 +424,7 @@ bool X86Subtarget::enablePostRAScheduler( CodeGenOpt::Level OptLevel, TargetSubtargetInfo::AntiDepBreakMode& Mode, RegClassVector& CriticalPathRCs) const { - //TODO: change back to ANTIDEP_CRITICAL when the - // X86 subtarget properly sets up post RA liveness. - Mode = TargetSubtargetInfo::ANTIDEP_NONE; + Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL; CriticalPathRCs.clear(); return PostRAScheduler && OptLevel >= CodeGenOpt::Default; } diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h index 7fd832bf06..766f2daccb 100644 --- a/lib/Target/X86/X86Subtarget.h +++ b/lib/Target/X86/X86Subtarget.h @@ -307,6 +307,8 @@ public: TargetSubtargetInfo::AntiDepBreakMode& Mode, RegClassVector& CriticalPathRCs) const; + bool postRAScheduler() const { return PostRAScheduler; } + /// getInstrItins = Return the instruction itineraries based on the /// subtarget selection. const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp index 6812f8f56d..cdd0a0893b 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -92,6 +92,11 @@ XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { } bool +XCoreRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { + return requiresRegisterScavenging(MF); +} + +bool XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const { return false; } diff --git a/lib/Target/XCore/XCoreRegisterInfo.h b/lib/Target/XCore/XCoreRegisterInfo.h index 7391cfdf07..c4dcb6b533 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.h +++ b/lib/Target/XCore/XCoreRegisterInfo.h @@ -50,6 +50,8 @@ public: bool requiresRegisterScavenging(const MachineFunction &MF) const; + bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const; + bool useFPForScavengingIndex(const MachineFunction &MF) const; void eliminateCallFramePseudoInstr(MachineFunction &MF, |