diff options
Diffstat (limited to 'lib')
23 files changed, 263 insertions, 56 deletions
diff --git a/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp b/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp index dc843856cd..5ac455e1a1 100644 --- a/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp +++ b/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/TargetAsmParser.h" #include "llvm/Target/TargetMachine.h" @@ -112,11 +113,15 @@ void AsmPrinter::EmitInlineAsm(StringRef Str, const MDNode *LocMDNode) const { OutContext, OutStreamer, *MAI)); - OwningPtr<TargetAsmParser> - TAP(TM.getTarget().createAsmParser(TM.getTargetTriple(), - TM.getTargetCPU(), - TM.getTargetFeatureString(), - *Parser)); + // FIXME: It would be nice if we can avoid createing a new instance of + // MCSubtargetInfo here given TargetSubtargetInfo is available. However, + // we have to watch out for asm directives which can change subtarget + // state. e.g. .code 16, .code 32. + OwningPtr<MCSubtargetInfo> + STI(TM.getTarget().createMCSubtargetInfo(TM.getTargetTriple(), + TM.getTargetCPU(), + TM.getTargetFeatureString())); + OwningPtr<TargetAsmParser> TAP(TM.getTarget().createAsmParser(*STI, *Parser)); if (!TAP) report_fatal_error("Inline asm not supported by this streamer because" " we don't have an asm parser for this target\n"); diff --git a/lib/MC/MCDisassembler/EDDisassembler.cpp b/lib/MC/MCDisassembler/EDDisassembler.cpp index a39f002a32..77c959f671 100644 --- a/lib/MC/MCDisassembler/EDDisassembler.cpp +++ b/lib/MC/MCDisassembler/EDDisassembler.cpp @@ -23,6 +23,7 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCParser/AsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" @@ -373,7 +374,8 @@ int EDDisassembler::parseInst(SmallVectorImpl<MCParsedAsmOperand*> &operands, *AsmInfo)); StringRef triple = tripleFromArch(Key.Arch); - OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(triple, "", "", + OwningPtr<MCSubtargetInfo> STI(Tgt->createMCSubtargetInfo(triple, "", "")); + OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(*STI, *genericParser)); AsmToken OpcodeToken = genericParser->Lex(); diff --git a/lib/MC/MCSubtargetInfo.cpp b/lib/MC/MCSubtargetInfo.cpp index 3bb20b07f3..b1b86fe61e 100644 --- a/lib/MC/MCSubtargetInfo.cpp +++ b/lib/MC/MCSubtargetInfo.cpp @@ -48,6 +48,23 @@ uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) { return FeatureBits; } +/// ToggleFeature - Toggle a feature and returns the re-computed feature +/// bits. This version does not change the implied bits. +uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) { + FeatureBits ^= FB; + return FeatureBits; +} + +/// ToggleFeature - Toggle a feature and returns the re-computed feature +/// bits. This version will also change all implied bits. +uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) { + SubtargetFeatures Features; + FeatureBits = Features.ToggleFeature(FeatureBits, FS, + ProcFeatures, NumFeatures); + return FeatureBits; +} + + InstrItineraryData MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const { assert(ProcItins && "Instruction itineraries information not available!"); diff --git a/lib/MC/SubtargetFeature.cpp b/lib/MC/SubtargetFeature.cpp index 951e0aa5b6..348cd4c9ab 100644 --- a/lib/MC/SubtargetFeature.cpp +++ b/lib/MC/SubtargetFeature.cpp @@ -224,6 +224,38 @@ void ClearImpliedBits(uint64_t &Bits, const SubtargetFeatureKV *FeatureEntry, } } +/// ToggleFeature - Toggle a feature and returns the newly updated feature +/// bits. +uint64_t +SubtargetFeatures::ToggleFeature(uint64_t Bits, const StringRef Feature, + const SubtargetFeatureKV *FeatureTable, + size_t FeatureTableSize) { + // Find feature in table. + const SubtargetFeatureKV *FeatureEntry = + Find(StripFlag(Feature), FeatureTable, FeatureTableSize); + // If there is a match + if (FeatureEntry) { + if ((Bits & FeatureEntry->Value) == FeatureEntry->Value) { + Bits &= ~FeatureEntry->Value; + + // For each feature that implies this, clear it. + ClearImpliedBits(Bits, FeatureEntry, FeatureTable, FeatureTableSize); + } else { + Bits |= FeatureEntry->Value; + + // For each feature that this implies, set it. + SetImpliedBits(Bits, FeatureEntry, FeatureTable, FeatureTableSize); + } + } else { + errs() << "'" << Feature + << "' is not a recognized feature for this target" + << " (ignoring feature)\n"; + } + + return Bits; +} + + /// getFeatureBits - Get feature bits a CPU. /// uint64_t SubtargetFeatures::getFeatureBits(const StringRef CPU, diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index f927abbeda..d8fd809c4b 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -41,12 +41,8 @@ namespace { class ARMOperand; class ARMAsmParser : public TargetAsmParser { + MCSubtargetInfo &STI; MCAsmParser &Parser; - /// STI, ARM_STI, Thumb_STI - Subtarget info for ARM and Thumb modes. STI - /// points to either ARM_STI or Thumb_STI depending on the mode. - const MCSubtargetInfo *STI; - OwningPtr<const MCSubtargetInfo> ARM_STI; - OwningPtr<const MCSubtargetInfo> Thumb_STI; MCAsmParser &getParser() const { return Parser; } MCAsmLexer &getLexer() const { return Parser.getLexer(); } @@ -91,14 +87,14 @@ class ARMAsmParser : public TargetAsmParser { bool isThumb() const { // FIXME: Can tablegen auto-generate this? - return (STI->getFeatureBits() & ARM::ModeThumb) != 0; + return (STI.getFeatureBits() & ARM::ModeThumb) != 0; } bool isThumbOne() const { - return isThumb() && (STI->getFeatureBits() & ARM::FeatureThumb2) == 0; + return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; } void SwitchMode() { - STI = isThumb() ? ARM_STI.get() : Thumb_STI.get(); - setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); + unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); + setAvailableFeatures(FB); } /// @name Auto-generated Match Functions @@ -135,27 +131,12 @@ class ARMAsmParser : public TargetAsmParser { const SmallVectorImpl<MCParsedAsmOperand*> &); public: - ARMAsmParser(StringRef TT, StringRef CPU, StringRef FS, MCAsmParser &_Parser) - : TargetAsmParser(), Parser(_Parser) { + ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) + : TargetAsmParser(), STI(_STI), Parser(_Parser) { MCAsmParserExtension::Initialize(_Parser); - STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS); - // FIXME: Design a better way to create two subtargets with only difference - // being a feature change. - if (isThumb()) { - Thumb_STI.reset(STI); - assert(TT.startswith("thumb") && "Unexpected Triple string for Thumb!"); - Twine ARM_TT = "arm" + TT.substr(5); - ARM_STI.reset(ARM_MC::createARMMCSubtargetInfo(ARM_TT.str(), CPU, FS)); - } else { - ARM_STI.reset(STI); - assert(TT.startswith("arm") && "Unexpected Triple string for ARM!"); - Twine Thumb_TT = "thumb" + TT.substr(3); - Thumb_STI.reset(ARM_MC::createARMMCSubtargetInfo(Thumb_TT.str(),CPU, FS)); - } - // Initialize the set of available features. - setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); + setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); } virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, @@ -2237,10 +2218,12 @@ bool ARMAsmParser::ParseDirectiveCode(SMLoc L) { Parser.Lex(); if (Val == 16) { - if (!isThumb()) SwitchMode(); + if (!isThumb()) + SwitchMode(); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); } else { - if (isThumb()) SwitchMode(); + if (isThumb()) + SwitchMode(); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); } diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index 0a8e3b171d..1139cac394 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -112,17 +112,18 @@ MCRegisterInfo *createARMMCRegisterInfo() { // Force static initialization. extern "C" void LLVMInitializeARMMCInstrInfo() { - RegisterMCInstrInfo<MCInstrInfo> X(TheARMTarget); - RegisterMCInstrInfo<MCInstrInfo> Y(TheThumbTarget); - TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo); TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo); } extern "C" void LLVMInitializeARMMCRegInfo() { - RegisterMCRegInfo<MCRegisterInfo> X(TheARMTarget); - RegisterMCRegInfo<MCRegisterInfo> Y(TheThumbTarget); - TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo); TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo); } + +extern "C" void LLVMInitializeARMMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget, + ARM_MC::createARMMCSubtargetInfo); + TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget, + ARM_MC::createARMMCSubtargetInfo); +} diff --git a/lib/Target/Alpha/AlphaSubtarget.cpp b/lib/Target/Alpha/AlphaSubtarget.cpp index 75f5d8b4f9..ccdc490d81 100644 --- a/lib/Target/Alpha/AlphaSubtarget.cpp +++ b/lib/Target/Alpha/AlphaSubtarget.cpp @@ -13,6 +13,7 @@ #include "AlphaSubtarget.h" #include "Alpha.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -35,3 +36,15 @@ AlphaSubtarget::AlphaSubtarget(const std::string &TT, const std::string &CPU, // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUName); } + +MCSubtargetInfo *createAlphaMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitAlphaMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeAlphaMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheAlphaTarget, + createAlphaMCSubtargetInfo); +} diff --git a/lib/Target/Blackfin/BlackfinSubtarget.cpp b/lib/Target/Blackfin/BlackfinSubtarget.cpp index 7b3e4d7f8b..92914ae291 100644 --- a/lib/Target/Blackfin/BlackfinSubtarget.cpp +++ b/lib/Target/Blackfin/BlackfinSubtarget.cpp @@ -12,6 +12,8 @@ //===----------------------------------------------------------------------===// #include "BlackfinSubtarget.h" +#include "Blackfin.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -42,3 +44,15 @@ BlackfinSubtarget::BlackfinSubtarget(const std::string &TT, // Parse features string. ParseSubtargetFeatures(CPUName, FS); } + +MCSubtargetInfo *createBlackfinMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitBlackfinMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeBlackfinMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheBlackfinTarget, + createBlackfinMCSubtargetInfo); +} diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp index ec4020e213..c59497efc2 100644 --- a/lib/Target/CBackend/CBackend.cpp +++ b/lib/Target/CBackend/CBackend.cpp @@ -37,6 +37,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetRegistry.h" @@ -61,6 +62,10 @@ extern "C" void LLVMInitializeCBackendTarget() { RegisterTargetMachine<CTargetMachine> X(TheCBackendTarget); } +extern "C" void LLVMInitializeCBackendMCSubtargetInfo() { + RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheCBackendTarget); +} + namespace { class CBEMCAsmInfo : public MCAsmInfo { public: diff --git a/lib/Target/CMakeLists.txt b/lib/Target/CMakeLists.txt index f982316fc0..9c684a2265 100644 --- a/lib/Target/CMakeLists.txt +++ b/lib/Target/CMakeLists.txt @@ -54,3 +54,9 @@ configure_file( ${LLVM_MAIN_INCLUDE_DIR}/llvm/Config/Disassemblers.def.in ${LLVM_BINARY_DIR}/include/llvm/Config/Disassemblers.def ) + +# Produce llvm/Config/MCSubtargetInfos.def +configure_file( + ${LLVM_MAIN_INCLUDE_DIR}/llvm/Config/MCSubtargetInfos.def.in + ${LLVM_BINARY_DIR}/include/llvm/Config/MCSubtargtInfos.def + ) diff --git a/lib/Target/CellSPU/SPUSubtarget.cpp b/lib/Target/CellSPU/SPUSubtarget.cpp index d9835070fb..3ce96b81a9 100644 --- a/lib/Target/CellSPU/SPUSubtarget.cpp +++ b/lib/Target/CellSPU/SPUSubtarget.cpp @@ -14,6 +14,7 @@ #include "SPUSubtarget.h" #include "SPU.h" #include "SPURegisterInfo.h" +#include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/SmallVector.h" #define GET_SUBTARGETINFO_ENUM @@ -65,3 +66,15 @@ bool SPUSubtarget::enablePostRAScheduler( CriticalPathRCs.push_back(&SPU::VECREGRegClass); return OptLevel >= CodeGenOpt::Default; } + +MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitSPUMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeCellSPUMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheCellSPUTarget, + createSPUMCSubtargetInfo); +} diff --git a/lib/Target/CppBackend/CPPBackend.cpp b/lib/Target/CppBackend/CPPBackend.cpp index ae03725e4c..351f12225c 100644 --- a/lib/Target/CppBackend/CPPBackend.cpp +++ b/lib/Target/CppBackend/CPPBackend.cpp @@ -23,6 +23,7 @@ #include "llvm/Pass.h" #include "llvm/PassManager.h" #include "llvm/TypeSymbolTable.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" @@ -75,6 +76,10 @@ extern "C" void LLVMInitializeCppBackendTarget() { RegisterTargetMachine<CPPTargetMachine> X(TheCppBackendTarget); } +extern "C" void LLVMInitializeCppBackendMCSubtargetInfo() { + RegisterMCSubtargetInfo<MCSubtargetInfo> X(TheCppBackendTarget); +} + namespace { typedef std::vector<const Type*> TypeList; typedef std::map<const Type*,std::string> TypeMap; diff --git a/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp b/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp index a6fc147499..8759e0c5f2 100644 --- a/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp +++ b/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp @@ -63,8 +63,7 @@ class MBlazeAsmParser : public TargetAsmParser { public: - MBlazeAsmParser(StringRef TT, StringRef CPU, StringRef FS, - MCAsmParser &_Parser) + MBlazeAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) : TargetAsmParser(), Parser(_Parser) {} virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, diff --git a/lib/Target/MBlaze/MBlazeSubtarget.cpp b/lib/Target/MBlaze/MBlazeSubtarget.cpp index eb5e28f131..54935b1ec5 100644 --- a/lib/Target/MBlaze/MBlazeSubtarget.cpp +++ b/lib/Target/MBlaze/MBlazeSubtarget.cpp @@ -15,6 +15,7 @@ #include "MBlaze.h" #include "MBlazeRegisterInfo.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -62,3 +63,15 @@ enablePostRAScheduler(CodeGenOpt::Level OptLevel, CriticalPathRCs.push_back(&MBlaze::GPRRegClass); return HasItin && OptLevel >= CodeGenOpt::Default; } + +MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitMBlazeMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeMBlazeMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheMBlazeTarget, + createMBlazeMCSubtargetInfo); +} diff --git a/lib/Target/MSP430/MSP430Subtarget.cpp b/lib/Target/MSP430/MSP430Subtarget.cpp index dddfd2c70c..6c5156f6d7 100644 --- a/lib/Target/MSP430/MSP430Subtarget.cpp +++ b/lib/Target/MSP430/MSP430Subtarget.cpp @@ -13,6 +13,7 @@ #include "MSP430Subtarget.h" #include "MSP430.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -31,3 +32,15 @@ MSP430Subtarget::MSP430Subtarget(const std::string &TT, // Parse features string. ParseSubtargetFeatures(CPUName, FS); } + +MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitMSP430MCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeMSP430MCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheMSP430Target, + createMSP430MCSubtargetInfo); +} diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index a0cb71ee6d..b2b26521ff 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -13,6 +13,7 @@ #include "MipsSubtarget.h" #include "Mips.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -61,3 +62,15 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, HasCondMov = true; } } + +MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitMipsMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeMipsMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget, + createMipsMCSubtargetInfo); +} diff --git a/lib/Target/PTX/PTXSubtarget.cpp b/lib/Target/PTX/PTXSubtarget.cpp index 584c1d0295..a8a2ef7309 100644 --- a/lib/Target/PTX/PTXSubtarget.cpp +++ b/lib/Target/PTX/PTXSubtarget.cpp @@ -12,7 +12,9 @@ //===----------------------------------------------------------------------===// #include "PTXSubtarget.h" +#include "PTX.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -64,3 +66,18 @@ std::string PTXSubtarget::getPTXVersionString() const { case PTX_VERSION_2_3: return "2.3"; } } + + +MCSubtargetInfo *createPTXMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitPTXMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializePTXMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(ThePTX32Target, + createPTXMCSubtargetInfo); + TargetRegistry::RegisterMCSubtargetInfo(ThePTX64Target, + createPTXMCSubtargetInfo); +} diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp index d4861256a8..bd40063d1c 100644 --- a/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/lib/Target/PowerPC/PPCSubtarget.cpp @@ -15,6 +15,7 @@ #include "PPC.h" #include "llvm/GlobalValue.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetRegistry.h" #include <cstdlib> #define GET_SUBTARGETINFO_ENUM @@ -140,3 +141,17 @@ bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV, return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || GV->hasCommonLinkage() || isDecl; } + +MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitPPCMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializePowerPCMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(ThePPC32Target, + createPPCMCSubtargetInfo); + TargetRegistry::RegisterMCSubtargetInfo(ThePPC64Target, + createPPCMCSubtargetInfo); +} diff --git a/lib/Target/Sparc/SparcSubtarget.cpp b/lib/Target/Sparc/SparcSubtarget.cpp index 05cea2af0c..3513479814 100644 --- a/lib/Target/Sparc/SparcSubtarget.cpp +++ b/lib/Target/Sparc/SparcSubtarget.cpp @@ -12,6 +12,8 @@ //===----------------------------------------------------------------------===// #include "SparcSubtarget.h" +#include "Sparc.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -42,3 +44,15 @@ SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, // Parse features string. ParseSubtargetFeatures(CPUName, FS); } + +MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitSparcMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeSparcMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheSparcTarget, + createSparcMCSubtargetInfo); +} diff --git a/lib/Target/SystemZ/SystemZSubtarget.cpp b/lib/Target/SystemZ/SystemZSubtarget.cpp index f20010b2b2..f6707f9a20 100644 --- a/lib/Target/SystemZ/SystemZSubtarget.cpp +++ b/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -15,6 +15,7 @@ #include "SystemZ.h" #include "llvm/GlobalValue.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -53,3 +54,15 @@ bool SystemZSubtarget::GVRequiresExtraLoad(const GlobalValue* GV, return false; } + +MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitSystemZMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeSystemZMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheSystemZTarget, + createSystemZMCSubtargetInfo); +} diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index db6ab33ed6..cdbbcd365f 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -37,8 +37,8 @@ namespace { struct X86Operand; class X86ATTAsmParser : public TargetAsmParser { + MCSubtargetInfo &STI; MCAsmParser &Parser; - OwningPtr<const MCSubtargetInfo> STI; private: MCAsmParser &getParser() const { return Parser; } @@ -66,7 +66,7 @@ private: bool is64Bit() { // FIXME: Can tablegen auto-generate this? - return (STI->getFeatureBits() & X86::Mode64Bit) != 0; + return (STI.getFeatureBits() & X86::Mode64Bit) != 0; } /// @name Auto-generated Matcher Functions @@ -78,13 +78,11 @@ private: /// } public: - X86ATTAsmParser(StringRef TT, StringRef CPU, StringRef FS, - MCAsmParser &parser) - : TargetAsmParser(), Parser(parser), - STI(X86_MC::createX86MCSubtargetInfo(TT, CPU, FS)) { + X86ATTAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser) + : TargetAsmParser(), STI(sti), Parser(parser) { // Initialize the set of available features. - setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits())); + setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); } virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); diff --git a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp index 728246ffa2..c34d3c92b7 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -145,17 +145,19 @@ MCRegisterInfo *createX86MCRegisterInfo() { // Force static initialization. extern "C" void LLVMInitializeX86MCInstrInfo() { - RegisterMCInstrInfo<MCInstrInfo> X(TheX86_32Target); - RegisterMCInstrInfo<MCInstrInfo> Y(TheX86_64Target); - TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo); TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo); } extern "C" void LLVMInitializeX86MCRegInfo() { - RegisterMCRegInfo<MCRegisterInfo> X(TheX86_32Target); - RegisterMCRegInfo<MCRegisterInfo> Y(TheX86_64Target); - TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo); TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo); } + + +extern "C" void LLVMInitializeX86MCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target, + X86_MC::createX86MCSubtargetInfo); + TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target, + X86_MC::createX86MCSubtargetInfo); +} diff --git a/lib/Target/XCore/XCoreSubtarget.cpp b/lib/Target/XCore/XCoreSubtarget.cpp index 7d8fe8a10b..8ede9366fc 100644 --- a/lib/Target/XCore/XCoreSubtarget.cpp +++ b/lib/Target/XCore/XCoreSubtarget.cpp @@ -13,6 +13,7 @@ #include "XCoreSubtarget.h" #include "XCore.h" +#include "llvm/Target/TargetRegistry.h" #define GET_SUBTARGETINFO_ENUM #define GET_SUBTARGETINFO_MC_DESC @@ -27,3 +28,16 @@ XCoreSubtarget::XCoreSubtarget(const std::string &TT, : XCoreGenSubtargetInfo(TT, CPU, FS) { } + + +MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitXCoreMCSubtargetInfo(X, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeXCoreMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheXCoreTarget, + createXCoreMCSubtargetInfo); +} |