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-rw-r--r--test/CodeGen/R600/store.ll90
1 files changed, 46 insertions, 44 deletions
diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll
index a4c025ab42..5e51d56917 100644
--- a/test/CodeGen/R600/store.ll
+++ b/test/CodeGen/R600/store.ll
@@ -7,7 +7,7 @@
;===------------------------------------------------------------------------===;
; i8 store
-; EG-CHECK: @store_i8
+; EG-CHECK-LABEL: @store_i8
; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
; EG-CHECK: VTX_READ_8 [[VAL:T[0-9]\.X]], [[VAL]]
; IG 0: Get the byte index and truncate the value
@@ -26,7 +26,7 @@
; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0
; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0
-; SI-CHECK: @store_i8
+; SI-CHECK-LABEL: @store_i8
; SI-CHECK: BUFFER_STORE_BYTE
define void @store_i8(i8 addrspace(1)* %out, i8 %in) {
@@ -36,7 +36,7 @@ entry:
}
; i16 store
-; EG-CHECK: @store_i16
+; EG-CHECK-LABEL: @store_i16
; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X
; EG-CHECK: VTX_READ_16 [[VAL:T[0-9]\.X]], [[VAL]]
; IG 0: Get the byte index and truncate the value
@@ -55,7 +55,7 @@ entry:
; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0
; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0
-; SI-CHECK: @store_i16
+; SI-CHECK-LABEL: @store_i16
; SI-CHECK: BUFFER_STORE_SHORT
define void @store_i16(i16 addrspace(1)* %out, i16 %in) {
entry:
@@ -63,10 +63,10 @@ entry:
ret void
}
-; EG-CHECK: @store_v2i8
+; EG-CHECK-LABEL: @store_v2i8
; EG-CHECK: MEM_RAT MSKOR
; EG-CHECK-NOT: MEM_RAT MSKOR
-; SI-CHECK: @store_v2i8
+; SI-CHECK-LABEL: @store_v2i8
; SI-CHECK: BUFFER_STORE_BYTE
; SI-CHECK: BUFFER_STORE_BYTE
define void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) {
@@ -77,12 +77,13 @@ entry:
}
-; EG-CHECK: @store_v2i16
+; EG-CHECK-LABEL: @store_v2i16
; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
-; CM-CHECK: @store_v2i16
+; CM-CHECK-LABEL: @store_v2i16
; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
-; SI-CHECK: @store_v2i16
-; SI-CHECK: BUFFER_STORE_DWORD
+; SI-CHECK-LABEL: @store_v2i16
+; SI-CHECK: BUFFER_STORE_SHORT
+; SI-CHECK: BUFFER_STORE_SHORT
define void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) {
entry:
%0 = trunc <2 x i32> %in to <2 x i16>
@@ -90,11 +91,11 @@ entry:
ret void
}
-; EG-CHECK: @store_v4i8
+; EG-CHECK-LABEL: @store_v4i8
; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
-; CM-CHECK: @store_v4i8
+; CM-CHECK-LABEL: @store_v4i8
; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
-; SI-CHECK: @store_v4i8
+; SI-CHECK-LABEL: @store_v4i8
; SI-CHECK: BUFFER_STORE_BYTE
; SI-CHECK: BUFFER_STORE_BYTE
; SI-CHECK: BUFFER_STORE_BYTE
@@ -107,11 +108,11 @@ entry:
}
; floating-point store
-; EG-CHECK: @store_f32
+; EG-CHECK-LABEL: @store_f32
; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1
-; CM-CHECK: @store_f32
+; CM-CHECK-LABEL: @store_f32
; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
-; SI-CHECK: @store_f32
+; SI-CHECK-LABEL: @store_f32
; SI-CHECK: BUFFER_STORE_DWORD
define void @store_f32(float addrspace(1)* %out, float %in) {
@@ -119,13 +120,13 @@ define void @store_f32(float addrspace(1)* %out, float %in) {
ret void
}
-; EG-CHECK: @store_v4i16
+; EG-CHECK-LABEL: @store_v4i16
; EG-CHECK: MEM_RAT MSKOR
; EG-CHECK: MEM_RAT MSKOR
; EG-CHECK: MEM_RAT MSKOR
; EG-CHECK: MEM_RAT MSKOR
; EG-CHECK-NOT: MEM_RAT MSKOR
-; SI-CHECK: @store_v4i16
+; SI-CHECK-LABEL: @store_v4i16
; SI-CHECK: BUFFER_STORE_SHORT
; SI-CHECK: BUFFER_STORE_SHORT
; SI-CHECK: BUFFER_STORE_SHORT
@@ -139,11 +140,11 @@ entry:
}
; vec2 floating-point stores
-; EG-CHECK: @store_v2f32
+; EG-CHECK-LABEL: @store_v2f32
; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
-; CM-CHECK: @store_v2f32
+; CM-CHECK-LABEL: @store_v2f32
; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
-; SI-CHECK: @store_v2f32
+; SI-CHECK-LABEL: @store_v2f32
; SI-CHECK: BUFFER_STORE_DWORDX2
define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) {
@@ -154,13 +155,13 @@ entry:
ret void
}
-; EG-CHECK: @store_v4i32
+; EG-CHECK-LABEL: @store_v4i32
; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
; EG-CHECK-NOT: MEM_RAT_CACHELESS STORE_RAW
-; CM-CHECK: @store_v4i32
+; CM-CHECK-LABEL: @store_v4i32
; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
; CM-CHECK-NOT: MEM_RAT_CACHELESS STORE_DWORD
-; SI-CHECK: @store_v4i32
+; SI-CHECK-LABEL: @store_v4i32
; SI-CHECK: BUFFER_STORE_DWORDX4
define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
entry:
@@ -172,41 +173,42 @@ entry:
; Local Address Space
;===------------------------------------------------------------------------===;
-; EG-CHECK: @store_local_i8
+; EG-CHECK-LABEL: @store_local_i8
; EG-CHECK: LDS_BYTE_WRITE
-; SI-CHECK: @store_local_i8
+; SI-CHECK-LABEL: @store_local_i8
; SI-CHECK: DS_WRITE_B8
define void @store_local_i8(i8 addrspace(3)* %out, i8 %in) {
store i8 %in, i8 addrspace(3)* %out
ret void
}
-; EG-CHECK: @store_local_i16
+; EG-CHECK-LABEL: @store_local_i16
; EG-CHECK: LDS_SHORT_WRITE
-; SI-CHECK: @store_local_i16
+; SI-CHECK-LABEL: @store_local_i16
; SI-CHECK: DS_WRITE_B16
define void @store_local_i16(i16 addrspace(3)* %out, i16 %in) {
store i16 %in, i16 addrspace(3)* %out
ret void
}
-; EG-CHECK: @store_local_v2i16
+; EG-CHECK-LABEL: @store_local_v2i16
; EG-CHECK: LDS_WRITE
-; CM-CHECK: @store_local_v2i16
+; CM-CHECK-LABEL: @store_local_v2i16
; CM-CHECK: LDS_WRITE
-; SI-CHECK: @store_local_v2i16
-; SI-CHECK: DS_WRITE_B32
+; SI-CHECK-LABEL: @store_local_v2i16
+; SI-CHECK: DS_WRITE_B16
+; SI-CHECK: DS_WRITE_B16
define void @store_local_v2i16(<2 x i16> addrspace(3)* %out, <2 x i16> %in) {
entry:
store <2 x i16> %in, <2 x i16> addrspace(3)* %out
ret void
}
-; EG-CHECK: @store_local_v4i8
+; EG-CHECK-LABEL: @store_local_v4i8
; EG-CHECK: LDS_WRITE
-; CM-CHECK: @store_local_v4i8
+; CM-CHECK-LABEL: @store_local_v4i8
; CM-CHECK: LDS_WRITE
-; SI-CHECK: @store_local_v4i8
+; SI-CHECK-LABEL: @store_local_v4i8
; SI-CHECK: DS_WRITE_B8
; SI-CHECK: DS_WRITE_B8
; SI-CHECK: DS_WRITE_B8
@@ -217,13 +219,13 @@ entry:
ret void
}
-; EG-CHECK: @store_local_v2i32
+; EG-CHECK-LABEL: @store_local_v2i32
; EG-CHECK: LDS_WRITE
; EG-CHECK: LDS_WRITE
-; CM-CHECK: @store_local_v2i32
+; CM-CHECK-LABEL: @store_local_v2i32
; CM-CHECK: LDS_WRITE
; CM-CHECK: LDS_WRITE
-; SI-CHECK: @store_local_v2i32
+; SI-CHECK-LABEL: @store_local_v2i32
; SI-CHECK: DS_WRITE_B32
; SI-CHECK: DS_WRITE_B32
define void @store_local_v2i32(<2 x i32> addrspace(3)* %out, <2 x i32> %in) {
@@ -232,17 +234,17 @@ entry:
ret void
}
-; EG-CHECK: @store_local_v4i32
+; EG-CHECK-LABEL: @store_local_v4i32
; EG-CHECK: LDS_WRITE
; EG-CHECK: LDS_WRITE
; EG-CHECK: LDS_WRITE
; EG-CHECK: LDS_WRITE
-; CM-CHECK: @store_local_v4i32
+; CM-CHECK-LABEL: @store_local_v4i32
; CM-CHECK: LDS_WRITE
; CM-CHECK: LDS_WRITE
; CM-CHECK: LDS_WRITE
; CM-CHECK: LDS_WRITE
-; SI-CHECK: @store_local_v4i32
+; SI-CHECK-LABEL: @store_local_v4i32
; SI-CHECK: DS_WRITE_B32
; SI-CHECK: DS_WRITE_B32
; SI-CHECK: DS_WRITE_B32
@@ -260,11 +262,11 @@ entry:
; Evergreen / Northern Islands don't support 64-bit stores yet, so there should
; be two 32-bit stores.
-; EG-CHECK: @vecload2
+; EG-CHECK-LABEL: @vecload2
; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW
-; CM-CHECK: @vecload2
+; CM-CHECK-LABEL: @vecload2
; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD
-; SI-CHECK: @vecload2
+; SI-CHECK-LABEL: @vecload2
; SI-CHECK: BUFFER_STORE_DWORDX2
define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
entry:
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-28 21:43:34 +0000