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-rw-r--r--test/CodeGen/SystemZ/shift-10.ll12
1 files changed, 12 insertions, 0 deletions
diff --git a/test/CodeGen/SystemZ/shift-10.ll b/test/CodeGen/SystemZ/shift-10.ll
index 3fd965745e..46ed2180df 100644
--- a/test/CodeGen/SystemZ/shift-10.ll
+++ b/test/CodeGen/SystemZ/shift-10.ll
@@ -64,3 +64,15 @@ define i64 @f5(i32 %a) {
%or = or i64 %shl, 7
ret i64 %or
}
+
+; Test that SRA gets replaced with SRL if the sign bit is the only one
+; that matters.
+define i64 @f6(i64 %a) {
+; CHECK-LABEL: f6:
+; CHECK: risbg %r2, %r2, 55, 183, 19
+; CHECK: br %r14
+ %shl = shl i64 %a, 10
+ %shr = ashr i64 %shl, 60
+ %and = and i64 %shr, 256
+ ret i64 %and
+}