summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAge
* Update Release Notesrelease-3.4Tom Stellard2014-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@209031 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r208908:Tom Stellard2014-05-15
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r208908 | thomas.stellard | 2014-05-15 15:50:25 -0400 (Thu, 15 May 2014) | 7 lines autoconf: Fix libLLVM-Major-Minor-Patch.so symlink The symlink needs to point to a relative path, so we don't break building in a chroot. Tested-by: Laurent Carlier <lordheavym@gmail.org> ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@208917 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r208501:Tom Stellard2014-05-15
| | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r208501 | hfinkel | 2014-05-11 12:23:29 -0400 (Sun, 11 May 2014) | 9 lines [PowerPC] On PPC32, 128-bit shifts might be runtime calls The counter-loops formation pass needs to know what operations might be function calls (because they can't appear in counter-based loops). On PPC32, 128-bit shifts might be runtime calls (even though you can't use __int128 on PPC32, it seems that SROA might form them). Fixes PR19709. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@208916 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r208721:Tom Stellard2014-05-15
| | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r208721 | thomas.stellard | 2014-05-13 15:37:03 -0400 (Tue, 13 May 2014) | 11 lines autoconf: Fix soname for libLLVM-Major.Minor.so (2nd try) We were using libLLVM-Major.Minor.Patch.so for the soname, but we need the soname to stay consistent for all Major.Minor.* releases otherwise operating system distributors will need to rebuild all packages that link with LLVM every time there is a new point release. This patch also reverses the compatibility symlink, so libLLVM-Major.Minor.Patch.so is now a symlink that points to libLLVM-Major-Minor.so. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@208829 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r207990:Tom Stellard2014-05-15
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r207990 | marek.olsak | 2014-05-05 15:30:54 -0400 (Mon, 05 May 2014) | 6 lines R600/SI: allow 5 more input SGPRs to a shader Our OpenGL driver needs 22 SGPRs (16 user SGPRs + 6 streamout non-user SGPRs). Signed-off-by: Marek Olšák <marek.olsak@amd.com> ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@208828 91177308-0d34-0410-b5e6-96231b3b80d8
* Bump version to 3.4.2Tom Stellard2014-05-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@208597 91177308-0d34-0410-b5e6-96231b3b80d8
* Update Release Notes for 3.4.1Tom Stellard2014-05-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@208596 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r203581:Tom Stellard2014-04-11
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r203581 | hans | 2014-03-11 11:49:24 -0400 (Tue, 11 Mar 2014) | 7 lines X86: Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059) This fixes the bug where we would bitcast the 64-bit floating point result of cmpneqsd to a 64-bit integer even on 32-bit targets. Differential Revision: http://llvm-reviews.chandlerc.com/D3009 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206071 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r198937:Tom Stellard2014-04-11
| | | | | | | | | | | ------------------------------------------------------------------------ r198937 | kristof.beyls | 2014-01-10 08:41:49 -0500 (Fri, 10 Jan 2014) | 2 lines Make sure -use-init-array has intended effect on all AArch64 ELF targets, not just linux. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206065 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r202774:Tom Stellard2014-04-11
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r202774 | reid | 2014-03-03 19:33:17 -0500 (Mon, 03 Mar 2014) | 7 lines MC: Fix Intel assembly parser for [global + offset] We were dropping the displacement on the floor if we also had some immediate offset. Should fix PR19033. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206061 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r201126:Tom Stellard2014-04-11
| | | | | | | | | | | ------------------------------------------------------------------------ r201126 | craig.topper | 2014-02-10 23:05:33 -0500 (Mon, 10 Feb 2014) | 2 lines Changed attributes of all gather intrinsics from IntrReadMem to IntrReadArgMem as they access only memory based on argument. Patch by Robert Khasanov. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206057 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r201507:Tom Stellard2014-04-11
| | | | | | | | | | | ------------------------------------------------------------------------ r201507 | craig.topper | 2014-02-17 05:03:43 -0500 (Mon, 17 Feb 2014) | 2 lines Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206056 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r205067:Tom Stellard2014-04-11
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r205067 | ahatanaka | 2014-03-28 19:28:07 -0400 (Fri, 28 Mar 2014) | 7 lines [x86] Fix printing of register operands with q modifier. Emit 32-bit register names instead of 64-bit register names if the target does not have 64-bit general purpose registers. <rdar://problem/14653996> ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206055 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200028:Tom Stellard2014-04-11
| | | | | | | | | | | | | ------------------------------------------------------------------------ r200028 | benny.kra | 2014-01-24 14:02:37 -0500 (Fri, 24 Jan 2014) | 4 lines InstCombine: Don't try to use aggregate elements of ConstantExprs. PR18600. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206054 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r199351:Tom Stellard2014-04-11
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r199351 | aschwaighofer | 2014-01-15 23:53:18 -0500 (Wed, 15 Jan 2014) | 5 lines BasicAA: We need to check both access sizes when comparing a gep and an underlying object of unknown size. Fixes PR18460. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206053 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r198400:Tom Stellard2014-04-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r198400 | aschwaighofer | 2014-01-03 00:47:03 -0500 (Fri, 03 Jan 2014) | 18 lines BasicAA: Use reachabilty instead of dominance for checking value equality in phi cycles This allows the value equality check to work even if we don't have a dominator tree. Also add some more comments. I was worried about compile time impacts and did not implement reachability but used the dominance check in the initial patch. The trade-off was that the dominator tree was required. The llvm utility function isPotentiallyReachable cuts off the recursive search after 32 visits. Testing did not show any compile time regressions showing my worries unjustfied. No compile time or performance regressions at O3 -flto -mavx on test-suite + externals. Addresses review comments from r198290. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206052 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r198290:Tom Stellard2014-04-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r198290 | aschwaighofer | 2014-01-01 22:31:36 -0500 (Wed, 01 Jan 2014) | 23 lines BasicAA: Fix value equality and phi cycles When there are cycles in the value graph we have to be careful interpreting "Value*" identity as "value" equivalence. We interpret the value of a phi node as the value of its operands. When we check for value equivalence now we make sure that the "Value*" dominates all cycles (phis). %0 = phi [%noaliasval, %addr2] %l = load %ptr %addr1 = gep @a, 0, %l %addr2 = gep @a, 0, (%l + 1) store %ptr ... Before this patch we would return NoAlias for (%0, %addr1) which is wrong because the value of the load is from different iterations of the loop. Tested on x86_64 -mavx at O3 and O3 -flto with no performance or compile time regressions. PR18068 radar://15653794 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206051 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196970:Tom Stellard2014-04-11
| | | | | | | | | | | | ------------------------------------------------------------------------ r196970 | fang | 2013-12-10 16:37:41 -0500 (Tue, 10 Dec 2013) | 3 lines on darwin<10, fallback to .weak_definition (PPC,X86) .weak_def_can_be_hidden was not yet supported by the system assembler ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206050 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195971:Tom Stellard2014-04-11
| | | | | | | | | | | ------------------------------------------------------------------------ r195971 | juergen | 2013-11-29 22:07:16 -0500 (Fri, 29 Nov 2013) | 2 lines Force CPU type to unbreak unit tests on Haswell machines. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@206049 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200705:Tom Stellard2014-04-09
| | | | | | | | | | | | ------------------------------------------------------------------------ r200705 | hfinkel | 2014-02-03 12:27:25 -0500 (Mon, 03 Feb 2014) | 5 lines Expand vector bswap in LegalizeVectorOps ISD::BSWAP was missing from the list of node types that should be expanded element-wise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205910 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r205630:Tom Stellard2014-04-09
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r205630 | hfinkel | 2014-04-04 11:15:57 -0400 (Fri, 04 Apr 2014) | 6 lines [PowerPC] Add a full condition code register to make the "cc" clobber work gcc inline asm supports specifying "cc" as a clobber of all condition registers. Add just enough modeling of the full register to make this work. Fixed PR19326. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205908 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r204304:Tom Stellard2014-04-09
| | | | | | | | | | | ------------------------------------------------------------------------ r204304 | Hao.Liu | 2014-03-20 01:36:59 -0400 (Thu, 20 Mar 2014) | 2 lines [ARM]Fix an assertion failure in A15SDOptimizer about DPair reg class by treating DPair as QPR. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205904 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r201841:Tom Stellard2014-04-09
| | | | | | | | | | | ------------------------------------------------------------------------ r201841 | Kevin.Qin | 2014-02-21 02:45:48 -0500 (Fri, 21 Feb 2014) | 2 lines [AArch64] Add register constraints to avoid generating STLXR and STXR with unpredictable behavior. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205903 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r201541:Tom Stellard2014-04-09
| | | | | | | | | | | ------------------------------------------------------------------------ r201541 | jiangning.liu | 2014-02-17 21:37:42 -0500 (Mon, 17 Feb 2014) | 2 lines Fix a typo about lowering AArch64 va_copy. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205902 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r199369:Tom Stellard2014-04-09
| | | | | | | | | | | ------------------------------------------------------------------------ r199369 | jiangning.liu | 2014-01-16 04:16:13 -0500 (Thu, 16 Jan 2014) | 2 lines For ARM, fix assertuib failures for some ld/st 3/4 instruction with wirteback. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205901 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r204155:Tom Stellard2014-04-09
| | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r204155 | wschmidt | 2014-03-18 10:32:50 -0400 (Tue, 18 Mar 2014) | 16 lines Fix PR19144: Incorrect offset generated for int-to-fp conversion at -O0. When converting a signed 32-bit integer to double-precision floating point on hardware without a lfiwax instruction, we have to instead use a lfd followed by fcfid. We were erroneously offsetting the address by 4 bytes in preparation for either a lfiwax or lfiwzx when generating the lfd. This fixes that silly error. This was not caught in the test suite since the conversion tests were run with -mcpu=pwr7, which implies availability of lfiwax. I've added another test case for older hardware that checks the code we expect in the absence of lfiwax and other flavors of fcfid. There are fewer tests in this test case because we punt to DAG selection in more cases on older hardware. (We must generate complex fiddly sequences in those cases, and there is marginal benefit in duplicating that logic in fast-isel.) ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205824 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r203054:Tom Stellard2014-04-09
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r203054 | hfinkel | 2014-03-05 20:28:23 -0500 (Wed, 05 Mar 2014) | 7 lines The PPC global base register cannot be r0 The global base register cannot be r0 because it might end up as the first argument to addi or addis. Fixes PR18316. I don't have a small stable test case. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205823 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r202192:Tom Stellard2014-04-09
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r202192 | hfinkel | 2014-02-25 15:51:50 -0500 (Tue, 25 Feb 2014) | 5 lines Account for 128-bit integer operations in PPCCTRLoops We need to abort the formation of counter-register-based loops where there are 128-bit integer operations that might become function calls. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205822 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200288:Tom Stellard2014-04-09
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r200288 | hfinkel | 2014-01-28 00:32:58 -0500 (Tue, 28 Jan 2014) | 5 lines Handle spilling the PPC GPRC_NOR0 register class GPRC_NOR0 is not a subclass of GPRC (because it also contains the ZERO pseudo register). As a result, we also need to check for it in the spilling code. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205821 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r199832:Tom Stellard2014-04-09
| | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r199832 | rafael.espindola | 2014-01-22 15:20:52 -0500 (Wed, 22 Jan 2014) | 11 lines Fix pr18515. My understanding (from reading just the llvm code) is that * most ppc cpus have a "sync n" instruction and an msync alias that is * "sync 0". * "book e" cpus instead have a msync instruction and not the more general "sync n" This patch reflects that in the .td files, allowing a single codepath for asm ond obj streamer and incidentelly fixes a crash when EmitRawText was called on a obj streamer. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205820 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r199763:Tom Stellard2014-04-09
| | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r199763 | hfinkel | 2014-01-21 15:15:58 -0500 (Tue, 21 Jan 2014) | 9 lines Fix pointer info on PPC byval stores For PPC64 SVR (and Darwin), the stores that take byval aggregate parameters from registers into the stack frame had MachinePointerInfo objects with incorrect offsets. These offsets are relative to the object itself, not to the stack frame base. This fixes self hosting on PPC64 when compiling with -enable-aa-sched-mi. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205819 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r199570:Tom Stellard2014-04-09
| | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r199570 | aschwaighofer | 2014-01-18 22:18:31 -0500 (Sat, 18 Jan 2014) | 11 lines LoopVectorizer: A reduction that has multiple uses of the reduction value is not a reduction. Really. Under certain circumstances (the use list of an instruction has to be set up right - hence the extra pass in the test case) we would not recognize when a value in a potential reduction cycle was used multiple times by the reduction cycle. Fixes PR18526. radar://15851149 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205818 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r198425:Tom Stellard2014-04-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r198425 | dpeixott | 2014-01-03 12:20:01 -0500 (Fri, 03 Jan 2014) | 33 lines Fix loop rerolling pass failure with non-consant loop lower bound The loop rerolling pass was failing with an assertion failure from a failed cast on loops like this: void foo(int *A, int *B, int m, int n) { for (int i = m; i < n; i+=4) { A[i+0] = B[i+0] * 4; A[i+1] = B[i+1] * 4; A[i+2] = B[i+2] * 4; A[i+3] = B[i+3] * 4; } } The code was casting the SCEV-expanded code for the new induction variable to a phi-node. When the loop had a non-constant lower bound, the SCEV expander would end the code expansion with an add insted of a phi node and the cast would fail. It looks like the cast to a phi node was only needed to get the induction variable value coming from the backedge to compute the end of loop condition. This patch changes the loop reroller to compare the induction variable to the number of times the backedge is taken instead of the iteration count of the loop. In other words, we stop the loop when the current value of the induction variable == IterationCount-1. Previously, the comparison was comparing the induction variable value from the next iteration == IterationCount. This problem only seems to occur on 32-bit targets. For some reason, the loop is not rerolled on 64-bit targets. PR18290 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205817 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r203146:Tom Stellard2014-04-08
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r203146 | reid | 2014-03-06 14:19:12 -0500 (Thu, 06 Mar 2014) | 6 lines MS asm: The initial dot in struct access is optional Fixes PR18994. Tests, once again, in that other repository. =P ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205814 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r205738:Tom Stellard2014-04-08
| | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r205738 | atrick | 2014-04-07 17:29:22 -0400 (Mon, 07 Apr 2014) | 16 lines Put a limit on ScheduleDAGSDNodes::ClusterNeighboringLoads to avoid blowing up compile time. Fixes PR16365 - Extremely slow compilation in -O1 and -O2. The SD scheduler has a quadratic implementation of load clustering which absolutely blows up compile time for large blocks with constant pool loads. The MI scheduler has a better implementation of load clustering. However, we have not done the work yet to completely eliminate the SD scheduler. Some benchmarks still seem to benefit from early load clustering, although maybe by chance. As an intermediate term fix, I just put a nice limit on the number of DAG users to search before finding a match. With this limit there are no binary differences in the LLVM test suite, and the PR16365 test case does not suffer any compile time impact from this routine. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205808 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200202:Tom Stellard2014-04-08
| | | | | | | | | | | ------------------------------------------------------------------------ r200202 | stpworld | 2014-01-27 04:43:10 -0500 (Mon, 27 Jan 2014) | 2 lines Additional fix for 200201: due to dependence on bitwidth test was moved to X86 directory. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205807 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r200201:Tom Stellard2014-04-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r200201 | stpworld | 2014-01-27 04:18:31 -0500 (Mon, 27 Jan 2014) | 31 lines Fix for PR18102. Issue outcomes from DAGCombiner::MergeConsequtiveStores, more precisely from mem-ops sequence sorting. Consider, how MergeConsequtiveStores works for next example: store i8 1, a[0] store i8 2, a[1] store i8 3, a[1] ; a[1] again. return ; DAG starts here 1. Method will collect all the 3 stores. 2. It sorts them by distance from the base pointer (farthest with highest index). 3. It takes first consecutive non-overlapping stores and (if possible) replaces them with a single store instruction. The point is, we can't determine here which 'store' instruction would be the second after sorting ('store 2' or 'store 3'). It happens that 'store 3' would be the second, and 'store 2' would be the third. So after merging we have the next result: store i16 (1 | 3 << 8), base ; is a[0] but bit-casted to i16 store i8 2, a[1] So actually we swapped 'store 3' and 'store 2' and got wrong contents in a[1]. Fix: In sort routine just also take into account mem-op sequence number. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205806 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r203725:Tom Stellard2014-04-08
| | | | | | | | | | | ------------------------------------------------------------------------ r203725 | rafael.espindola | 2014-03-12 18:03:43 -0400 (Wed, 12 Mar 2014) | 2 lines This test need the X86 backend, move it to the X86 sub directory. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205798 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r203719:Tom Stellard2014-04-08
| | | | | | | | | | | | | ------------------------------------------------------------------------ r203719 | mzolotukhin | 2014-03-12 17:31:05 -0400 (Wed, 12 Mar 2014) | 4 lines PR17473: Don't normalize an expression during postinc transformation unless it's invertible. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205797 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r202273:Tom Stellard2014-04-08
| | | | | | | | | | | | | ------------------------------------------------------------------------ r202273 | atrick | 2014-02-26 11:31:56 -0500 (Wed, 26 Feb 2014) | 4 lines Fix PR18165: LSR must avoid scaling factors that exceed the limit on truncated use. Patch by Michael Zolotukhin! ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205796 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r201104:Tom Stellard2014-04-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r201104 | chandlerc | 2014-02-10 14:39:35 -0500 (Mon, 10 Feb 2014) | 26 lines [LPM] A terribly simple fix to a terribly complex bug: PR18773. The crux of the issue is that LCSSA doesn't preserve stateful alias analyses. Before r200067, LICM didn't cause LCSSA to run in the LTO pass manager, where LICM runs essentially without any of the other loop passes. As a consequence the globalmodref-aa pass run before that loop pass manager was able to survive the loop pass manager and be used by DSE to eliminate stores in the function called from the loop body in Adobe-C++/loop_unroll (and similar patterns in other benchmarks). When LICM was taught to preserve LCSSA it had to require it as well. This caused it to be run in the loop pass manager and because it did not preserve AA, the stateful AA was lost. Most of LLVM's AA isn't stateful and so this didn't manifest in most cases. Also, in most cases LCSSA was already running, and so there was no interesting change. The real kicker is that LCSSA by its definition (injecting PHI nodes only) trivially preserves AA! All we need to do is mark it, and then everything goes back to working as intended. It probably was blocking some other weird cases of stateful AA but the only one I have is a 1000-line IR test case from loop_unroll, so I don't really have a good test case here. Hopefully this fixes the regressions on performance that have been seen since that revision. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205795 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r198863:Tom Stellard2014-04-08
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r198863 | stpworld | 2014-01-09 07:26:12 -0500 (Thu, 09 Jan 2014) | 6 lines Fixed old typo in ScalarEvolution, that caused wrong SCEVs zext operation. Detailed description is here: http://llvm.org/bugs/show_bug.cgi?id=18000#c16 For participation in bugfix process special thanks to David Wiberg. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205794 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r198744:Tom Stellard2014-04-08
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r198744 | iain | 2014-01-08 05:22:54 -0500 (Wed, 08 Jan 2014) | 8 lines [patch] Adjust behavior of FDE cross-section relocs for targets that don't support abs-differences. Modern versions of OSX/Darwin's ld (ld64 > 97.17) have an optimisation present that allows the back end to omit relocations (and replace them with an absolute difference) for FDE some text section refs. This patch allows a backend to opt-in to this behaviour by setting "DwarfFDESymbolsUseAbsDiff". At present, this is only enabled for modern x86 OSX ports. test changes by David Fang. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205768 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r197574:Tom Stellard2014-04-08
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r197574 | rafael.espindola | 2013-12-18 10:06:25 -0500 (Wed, 18 Dec 2013) | 8 lines Fix f64 and f128 for ppc-darwin. This patch adds -f64:32:64 to 32 bit ppc darwin since a f64 inside a structure are only 32 bit aligned. The patch also drop -f128:64:128 from all ppc darwin, since f128 is 128 bit aligned. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205767 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r197572:Tom Stellard2014-04-08
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r197572 | rafael.espindola | 2013-12-18 09:35:37 -0500 (Wed, 18 Dec 2013) | 6 lines One ppc32-darwin, a i64 inside a structure can have 32 bit alignment. Thanks for Iain Sandoe for testing this with the original gcc. Clang was already getting this right. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205766 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196987:Tom Stellard2014-04-08
| | | | | | | | | | | ------------------------------------------------------------------------ r196987 | rafael.espindola | 2013-12-10 19:09:06 -0500 (Tue, 10 Dec 2013) | 2 lines Move PPC's getDataLayoutString out of line and document it better. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205765 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196168:Tom Stellard2014-04-08
| | | | | | | | | | | ------------------------------------------------------------------------ r196168 | rafael.espindola | 2013-12-02 18:04:51 -0500 (Mon, 02 Dec 2013) | 2 lines Convert two char* that are only ever used as booleans to bool. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205764 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r203818:Tom Stellard2014-03-24
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r203818 | thomas.stellard | 2014-03-13 10:13:04 -0700 (Thu, 13 Mar 2014) | 7 lines R600: LDS instructions shouldn't implicitly define OQAP LDS instructions are pseudo instructions which model the OQAP defs and uses within a single instruction. This fixes a hang in the opencv MedianFilter tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204650 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r203281:Tom Stellard2014-03-24
| | | | | | | | | | | | ------------------------------------------------------------------------ r203281 | thomas.stellard | 2014-03-07 12:12:39 -0800 (Fri, 07 Mar 2014) | 4 lines R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCC Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204649 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r201097:Tom Stellard2014-03-24
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r201097 | thomas.stellard | 2014-02-10 08:58:30 -0800 (Mon, 10 Feb 2014) | 9 lines R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are used DS instructions that access local memory can only uses addresses that are less than or equal to the value of M0. When M0 is uninitialized, then we experience undefined behavior. This patch also changes the behavior to emit S_WQM_B64 on pixel shaders no matter what kind of DS instruction is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204648 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-25 23:34:01 +0000