summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAge
...
* Teach llvm-size to know about Mach-O universal files (aka fat files) andKevin Enderby2014-06-18
| | | | | | | | | | | fat files containing archives. Also fix a bug in MachOUniversalBinary::ObjectForArch::ObjectForArch() where it needed a >= when comparing the Index with the number of objects in a fat file. As the index starts at 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211230 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Handle fnearbyintMatt Arsenault2014-06-18
| | | | | | | | The difference from rint isn't really relevant here, so treat them as equivalent. OpenCL doesn't have nearbyint, so this is sort of pointless other than for completeness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211229 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: add gather4 and getlod intrinsics (v3)Marek Olsak2014-06-18
| | | | | | | | | | This contains all the previous patches + getlod support on top of it. It doesn't use SDNodes anymore, so it's quite small. It also adds v16i8 to SReg_128, which is used for the sampler descriptor. Reviewed-by: Tom Stellard git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211228 91177308-0d34-0410-b5e6-96231b3b80d8
* Use LL suffix for literal that should be 64-bits.Matt Arsenault2014-06-18
| | | | | | This hopefully fixes Windows git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211225 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a symbols() range and use a range loop.Rafael Espindola2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211222 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify code.Rafael Espindola2014-06-18
| | | | | | We can delete the objects earlier now that we are copying the names to a buffer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211221 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: do not add comment string to the AsmToken in AsmLexer::LexLineCommentSaleem Abdulrasool2014-06-18
| | | | | | | | Fixes macros with varargs if the macro instantiation has a trailing comment. Patch by Janne Grunau! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211219 91177308-0d34-0410-b5e6-96231b3b80d8
* MCAsmParser: full support for gas' '.if{cond} expression' directivesSaleem Abdulrasool2014-06-18
| | | | | | Patch by Janne Grunau! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211218 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace Execution Engine's mutex with std::recursive_mutex.Zachary Turner2014-06-18
| | | | | | | | | | | | | This change has a bit of a trickle down effect due to the fact that there are a number of derived implementations of ExecutionEngine, and that the mutex is not tightly encapsulated so is used by other classes directly. Reviewed by: rnk Differential Revision: http://reviews.llvm.org/D4196 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211214 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert a C API difference that I incorrectly introduced.Rafael Espindola2014-06-18
| | | | | | | LLVMGetBitcodeModuleInContext should not take ownership on error. I will try to localize this odd api requirement, but this should get the bots green. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211213 91177308-0d34-0410-b5e6-96231b3b80d8
* Make getBaseObject static.Rafael Espindola2014-06-18
| | | | | | Thanks to David Majnemer for noticing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211208 91177308-0d34-0410-b5e6-96231b3b80d8
* Change IRObjectFile to parse the bitcode lazily.Rafael Espindola2014-06-18
| | | | | | | The main point of this class is to provide a cheap object interface to a bitcode file, so it has to be as lazy as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211207 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove BitcodeReader::setBufferOwned.Rafael Espindola2014-06-18
| | | | | | | | | | We do have use cases for the bitcode reader owning the buffer or not, but we always know which one we have when we construct it. It might be possible to simplify this further, but this is a step in the right direction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211205 91177308-0d34-0410-b5e6-96231b3b80d8
* Simply test for available locations in optimization remarks.Diego Novillo2014-06-18
| | | | | | | | | | | | | | | | | When emitting optimization remarks, we test for the presence of instruction locations by testing for a valid llvm.dbg.cu annotation. This is slightly inefficient because we can simply ask whether the debug location we have is known or not. Additionally, if my current plan works, I will need to remove the llvm.dbg.cu annotation from the IL (or prevent it from being generated) when -Rpass is used without -g. In those cases, we'll want to generate line tables but we will want to prevent code generation from emitting DWARF code for them. Tested on x86_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211204 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Remove unnecessary load of r12 in indirect callUlrich Weigand2014-06-18
| | | | | | | | | | | | | | | | | When looking at the 64-bit SVR4 indirect call sequence, I noticed an unnecessary load of r12. And indeed the code says: // R12 must contain the address of an indirect callee. But this is not correct; in the 64-bit SVR4 (ELFv1) ABI, there is no need to load r12 at this point. It seems this code and comment is a remnant of code originally shared with the Darwin ABI ... This patch simply removes the unnecessary load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211203 91177308-0d34-0410-b5e6-96231b3b80d8
* Update to the latest registered ELF e_machine names and values.Rafael Espindola2014-06-18
| | | | | | Patch by John Wolf! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211202 91177308-0d34-0410-b5e6-96231b3b80d8
* Run clang-format in a small chunk of code I am about to change.Rafael Espindola2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211201 91177308-0d34-0410-b5e6-96231b3b80d8
* ProfileData: Fix copy-paste type in RawInstrProfReaderJustin Bogner2014-06-18
| | | | | | | | These deleted definitions had the wrong types. Patch by Alex L! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211199 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] [MC] Refactor the constant pool classesWeiming Zhao2014-06-18
| | | | | | | | | | | | | ARMTargetStreamer implements ConstantPool and AssmeblerConstantPools to keep track of assembler-generated constant pools that are used for ldr-pseudo. When implementing ldr-pseudo for AArch64, these two classes can be reused. So this patch factors them out from ARM target to the general MC lib. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211198 91177308-0d34-0410-b5e6-96231b3b80d8
* ADT: correct typo in commentEd Maste2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211196 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand vector fceilJan Vesely2014-06-18
| | | | | | | | | | Move fp64 fceil tests to fceil64.ll v2: rebase Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211194 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Simplify and improve loading into TOC registerUlrich Weigand2014-06-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During an indirect function call sequence on the 64-bit SVR4 ABI, generate code must load and then restore the TOC register. This does not use a regular LOAD instruction since the TOC register r2 is marked as reserved. Instead, the are two special instruction patterns: let RST = 2, DS = 2 in def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg), "ld 2, 8($reg)", IIC_LdStLD, [(PPCload_toc i64:$reg)]>, isPPC64; let RST = 2, DS = 10, RA = 1 in def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), "ld 2, 40(1)", IIC_LdStLD, [(PPCtoc_restore)]>, isPPC64; Note that these not only restrict the destination of the load to r2, but they also restrict the *source* of the load to particular address combinations. The latter is a problem when we want to support the ELFv2 ABI, since there the TOC save slot is no longer at 40(1). This patch replaces those two instructions with a single instruction pattern that only hard-codes r2 as destination, but supports generic addresses as source. This will allow supporting the ELFv2 ABI, and also helps generate more efficient code for calls to absolute addresses (allowing simplification of the ppc64-calls.ll test case). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211193 91177308-0d34-0410-b5e6-96231b3b80d8
* Work around ridiculous warning.Matt Arsenault2014-06-18
| | | | | | Apparently C++ doesn't really have hex floating point constants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211192 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add back test case for absolute calls (removed in r211174)Ulrich Weigand2014-06-18
| | | | | | | | | | As requested by Hal Finkel, this adds back a test for calls to a known-constant function pointer value, and verifies that the 64-bit SVR4 indirect function call sequence is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211190 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a triple so that right syntax is choosen on mac osx systemsArnold Schwaighofer2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211188 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add intrinsics for brev instructionsMatt Arsenault2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211187 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Prettier operand printing for 64-bit ops.Matt Arsenault2014-06-18
| | | | | | Copy what is done for 32-bit already so the order is about the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211186 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] SYNC $stype instruction was added in Mips32Matheus Almeida2014-06-18
| | | | | | | but SYNC with an implied operand ($stype = 0) is valid since Mips2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211185 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a memory leak in the error path.Rafael Espindola2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211184 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Implement f64 ftrunc, ffloor and fceil.Matt Arsenault2014-06-18
| | | | | | CI has instructions for these, so this fixes them for older hardware. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211183 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Custom lower f64 frint for pre-CIMatt Arsenault2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211182 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Temporary fix for f64 fnegMatt Arsenault2014-06-18
| | | | | | | This should be a source modifier, but this unblocks most of my math patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211181 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Comparisons set vcc.Matt Arsenault2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211178 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] AVX512: Add non-temporal storesAdam Nemet2014-06-18
| | | | | | | | | | | Note that I followed the AVX2 convention here and didn't add LLVM intrinsics for stores. These can be generated with the nontemporal hint on LLVM IR stores (see new test). The GCC builtins are lowered directly into nontemporal stores. <rdar://problem/17082571> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211176 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] AVX512: Specify compressed displacement for vmovntdqaAdam Nemet2014-06-18
| | | | | | | Use the max 64-bit element size with EVEX_CD8. This should work since element size is ignored for a full-vector access (FVM). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211175 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Do not use BLA with the 64-bit SVR4 ABIUlrich Weigand2014-06-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The PowerPC back-end uses BLA to implement calls to functions at known-constant addresses, which is apparently used for certain system routines on Darwin. However, with the 64-bit SVR4 ABI, this is actually incorrect. An immediate function pointer value on this platform is not directly usable as a target address for BLA: - in the ELFv1 ABI, the function pointer value refers to the *function descriptor*, not the code address - in the ELFv2 ABI, the function pointer value refers to the global entry point, but BL(A) would only be correct when calling the *local* entry point This bug didn't show up since using immediate function pointer values is not usually done in the 64-bit SVR4 ABI in the first place. However, I ran into this issue with a certain use case of LLVM as JIT, where immediate function pointer values were uses to implement callbacks from JITted code to helpers in statically compiled code. Fixed by simply not using BLA with the 64-bit SVR4 ABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211174 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not XFAIL test/tools/llvm-cov tests on powerpc64leUlrich Weigand2014-06-18
| | | | | | | | | | | | | All tests in test/tools/llvm-cov fail on big-endian targets and are supposed to be XFAILed there. However, including "powerpc64" in the XFAIL line is now incorrect, since that matches both powerpc64- and powerpc64le- targets, and the tests pass on the latter. Update the XFAIL lines to use powerpc64- instead (like mips64-). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211172 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Fix emitting instruction pairs on LEUlrich Weigand2014-06-18
| | | | | | | | | | | | | | | My patch r204634 to emit instructions in little-endian format failed to handle those special cases where we emit a pair of instructions from a single LLVM MC instructions (like the bl; nop pairs used to implement the call sequence). In those cases, we still need to emit the "first" instruction (the one in the more significant word) first, on both big and little endian, and not swap them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211171 91177308-0d34-0410-b5e6-96231b3b80d8
* Support LE in RelocVisitor::visitELF_PPC64_*Ulrich Weigand2014-06-18
| | | | | | | | | | Since we now support both LE and BE PPC64 variants, use of getAddend64BE is no longer correct. Use the generic getELFRelocationAddend instead, as was already done for Mips. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211170 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix expansion of memory operation if destination register is not a GPR.Matheus Almeida2014-06-18
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The assembler tries to reuse the destination register for memory operations whenever it can but it's not possible to do so if the destination register is not a GPR. Example: ldc1 $f0, sym should expand to: lui $at, %hi(sym) ldc1 $f0, %lo(sym)($at) It's entirely wrong to expand to: lui $f0, %hi(sym) ldc1 $f0, %lo(sym)($f0) Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4173 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211169 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Report correct location when "erroring" about the use of $at when ↵Matheus Almeida2014-06-18
| | | | | | | | | | | | | | it's not available. Summary: This removes the FIXMEs from test/MC/Mips/mips-noat.s. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4172 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211168 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] Add BLTC and BLTUC instructionsZoran Jovanovic2014-06-18
| | | | | | | Differential Revision: http://reviews.llvm.org/D3923 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211167 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Access $at only if necessary.Matheus Almeida2014-06-18
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch doesn't really change the logic behind expandMemInst but it allows us to assemble .S files that use .set noat with some macros. For example: .set noat lw $k0, offset($k1) Can expand to: lui $k0, %hi(offset) addu $k0, $k0, $k1 lw $k0, %lo(offset)($k0) with no need to access $at. Reviewers: dsanders, vmedic Reviewed By: dsanders, vmedic Differential Revision: http://reviews.llvm.org/D4159 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211165 91177308-0d34-0410-b5e6-96231b3b80d8
* Add pattern for unsigned v4i32->v4f64 convert on AVX512.Cameron McInally2014-06-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211164 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Update MipsAsmParser so that it's possible to handle immediates that ↵Matheus Almeida2014-06-18
| | | | | | | | | | | | start with the binary operator NOT (~). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4158 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211163 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Implement alias for 'and' and 'or' instructions for all ISAs.Matheus Almeida2014-06-18
| | | | | | | | | | | | | | | Summary: Examples: and $2, 4 <=> andi $2, $2, 4 or $2, 4 <=> ori $2, $2, 4 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4155 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211161 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Remove the last usage of parseRegister from MipsAsmParser.Matheus Almeida2014-06-18
| | | | | | | | | | | | | | Summary: Added negative test case so that we can be sure we handle erroneous situations while parsing the .cpsetup directive. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3681 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211160 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Implement 64bit SRAJan Vesely2014-06-18
| | | | | | | | v2: Use capitalized variable name Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211159 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Implement 64bit SRLJan Vesely2014-06-18
| | | | | | | | v2: use C++ style comment Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211158 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Implement 64bit SHLJan Vesely2014-06-18
| | | | | | | | v2: Use c++ style comment Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211157 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-30 08:54:01 +0000