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* Update cmake list.Devang Patel2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141104 91177308-0d34-0410-b5e6-96231b3b80d8
* Tell people using the tutorial how to make it actually work.David Chisnall2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141103 91177308-0d34-0410-b5e6-96231b3b80d8
* Test Operand ArgumentsDavid Greene2011-10-04
| | | | | | | | | Add a test to do list manipulation and pass the result as arguments. This tests the new list element operator resolve code and provides an example of using list manipulation to do instruction pattern substitution. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141102 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow Operator ArgumentsDavid Greene2011-10-04
| | | | | | | | | | | | | | | When resolving an operator list element reference, resolve all operator operands and try to fold the operator first. This allows the operator to collapse to a list which may then be indexed. Before, it was not possible to do this: class D<int a, int b> { ... } class C<list<int> A> : D<A[0], A[1]>; class B<list<int> b> : C<!foreach(...,b)>; Now it is. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141101 91177308-0d34-0410-b5e6-96231b3b80d8
* Un-XFAIL the file. Disable only the individual tests that aren't working yet.Jim Grosbach2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141099 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak CMake build.Ted Kremenek2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141097 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Formatting.Jim Grosbach2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141096 91177308-0d34-0410-b5e6-96231b3b80d8
* Put GCOVFile and other related interface in a common header so that llvm-cov ↵Devang Patel2011-10-04
| | | | | | tool can share it with GCOV writer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141095 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak MSVC build.Francois Pichet2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141093 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR9833/PR11054 (patch provided by Patrik Hägglund)David Dean2011-10-04
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* Teach TableGen to infer missing register classes.Jakob Stoklund Olesen2011-10-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The set of register classes should be closed under sub-register operations and intersections. That will allow the register allocator to model combinations of constraints accurately. This patch implements the easiest form of register class inference: For every register class, and for every sub-register SubIdx, the subset of registers in RC that have a SubIdx sub-register should also be a register class. This does create some new register classes for the targets in the tree: ARM gets a new QQQQPR_with_ssub_0. This class was omitted from the .td file on purpose because it only has two registers. InstrEmitter and RegisterCoalescer have safeguards against selecting too small register classes, so it is harmless. PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32 sub-register of LR8. I think that might be an omission? X86 puts RIP in the GR64 class, and since that register doesn't have 8-bit sub-registers, we get: GR64_with_sub_8bit GR64_TC_with_sub_8bit GR64_NOREX_with_sub_8bit GR64_TC_with_sub_8bit_hi The various CodeGen classes have already been fixed so adding new register classes should not affect compile time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141084 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach PPCInstrInfo to handle sub-classes.Jakob Stoklund Olesen2011-10-04
| | | | | | This has already been done for most other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141083 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Store all allocation orders together.Jakob Stoklund Olesen2011-10-04
| | | | | | There is no need to keep the primary order separate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141082 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Privatize CodeGenRegisterClass::TheDef and Name.Jakob Stoklund Olesen2011-10-04
| | | | | | | | When TableGen starts creating its own register classes, the synthesized classes won't have a Record reference. All register classes must have a name, though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141081 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Don't add synthetic Records to the RecordKeeper.Jakob Stoklund Olesen2011-10-04
| | | | | | | The RecordKeeper could be shared by multiple target instances, causing duplicate record errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141080 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen: add preprocessor as a separate modeChe-Liang Chiou2011-10-04
| | | | | | | | | | | | | | | | This patch adds a preprocessor that can expand nested for-loops for saving some copy-n-paste in *.td files. The preprocessor is not yet integrated with TGParser, and so it has no direct effect on *.td inputs. However, you may preprocess an td input (and only preprocess it). To test the proprecessor, type: tblgen -E -o $@ $< git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141079 91177308-0d34-0410-b5e6-96231b3b80d8
* Set operation actions to legal types only.Nadav Rotem2011-10-04
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* Operations should be custom lowered only if their type is legal.Nadav Rotem2011-10-04
| | | | | | | | Test: CellSPU/v2i32.ll when running with -promote-elements git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141074 91177308-0d34-0410-b5e6-96231b3b80d8
* The product of two chrec's can always be represented as a chrec.Nick Lewycky2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141066 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-04
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
* LSR should avoid redundant edge splitting.Andrew Trick2011-10-04
| | | | | | | | | This handles the case in which LSR rewrites an IV user that is a phi and splits critical edges originating from a switch. Fixes <rdar://problem/6453893> LSR is not splitting edges "nicely" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141059 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2011-10-04
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* Remove last references to hotpatch.Rafael Espindola2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141057 91177308-0d34-0410-b5e6-96231b3b80d8
* Exclude libLLVMTableGen.a from the shared libraryPeter Collingbourne2011-10-04
| | | | | | Unbreaks tools for --enable-shared build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141052 91177308-0d34-0410-b5e6-96231b3b80d8
* Generic cleanup.Bill Wendling2011-10-04
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* Unit test for r140919, loop unroll heuristics.Andrew Trick2011-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141049 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. These tests are covered in the .s file tests now.Jim Grosbach2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141047 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VMOV immediate.Jim Grosbach2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. 80 columns.Jim Grosbach2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141043 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the PC label ID rather than '1'. Add support for thumb-2, because I ↵Bill Wendling2011-10-03
| | | | | | heard that some people use it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141042 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't carry over the dispatchsetup hack from the old system.Bill Wendling2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141040 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM parsing/encoding for VCMP/VCMPE.Jim Grosbach2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo in comments.Nick Lewycky2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141032 91177308-0d34-0410-b5e6-96231b3b80d8
* Check-pointing the new SjLj EH lowering.Bill Wendling2011-10-03
| | | | | | | | | | | | This code will replace the version in ARMAsmPrinter.cpp. It creates a new machine basic block, which is the dispatch for the return from a longjmp call. It then shoves the address of that machine basic block into the correct place in the function context so that the EH runtime will jump to it directly instead of having to go through a compare-and-jump-to-the-dispatch bit. This should be more efficient in the common case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141031 91177308-0d34-0410-b5e6-96231b3b80d8
* Move CHECK after entry label.Akira Hatanaka2011-10-03
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* Add support for 64-bit logical NOR.Akira Hatanaka2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141029 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for 64-bit count leading ones and zeros instructions.Akira Hatanaka2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141028 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the grabbing of the jump buffer into the caller function, eliminating ↵Bill Wendling2011-10-03
| | | | | | the need for returning a std::pair. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141026 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VMRS/FMSTAT.Jim Grosbach2011-10-03
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* Add support for 64-bit divide instructions.Akira Hatanaka2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141024 91177308-0d34-0410-b5e6-96231b3b80d8
* Add C api for Instruction->eraseFromParent().Devang Patel2011-10-03
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* Update test for 141010.Jim Grosbach2011-10-03
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* Thumb2 ADD/SUB can take SP as a destination register.Jim Grosbach2011-10-03
| | | | | | | It's documented as a separate instruction to line up with the Thumb1 encodings, for which it really is a distinct instruction encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141020 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integerAkira Hatanaka2011-10-03
| | | | | | | | registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141019 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for 64-bit integer multiply instructions.Akira Hatanaka2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141017 91177308-0d34-0410-b5e6-96231b3b80d8
* Add definitions of instructions which move values between 64-bit integerAkira Hatanaka2011-10-03
| | | | | | | | | registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions of the instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141015 91177308-0d34-0410-b5e6-96231b3b80d8
* Find the strip tool that works with the specified SDKROOT. rdar://10165908Bob Wilson2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141013 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up a bit. Formatting.Jim Grosbach2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141010 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for MOVBE and RDRAND instructions for the assembler and ↵Craig Topper2011-10-03
| | | | | | disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace.Eric Christopher2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141005 91177308-0d34-0410-b5e6-96231b3b80d8
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