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* Make getObject const. Remove a const_cast.Rafael Espindola2013-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178980 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove last use of InMemoryStruct in llvm-objdump.Rafael Espindola2013-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178979 91177308-0d34-0410-b5e6-96231b3b80d8
* Most PPC M[TF]CR instructions do not have side effectsHal Finkel2013-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178978 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code.Rafael Espindola2013-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178977 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused argument.Rafael Espindola2013-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178976 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR15674 (and PR15603): a SROA think-o.Chandler Carruth2013-04-07
| | | | | | | | | | | | | | The fix for PR14972 in r177055 introduced a real think-o in the *store* side, likely because I was much more focused on the load side. While we can arbitrarily widen (or narrow) a loaded value, we can't arbitrarily widen a value to be stored, as that changes the width of memory access! Lock down the code path in the store rewriting which would do this to only handle the intended circumstance. All of the existing tests continue to pass, and I've added a test from the PR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178974 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC pre-increment load instructions do not have side effectsHal Finkel2013-04-07
| | | | | | A few were missed in r178972. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178973 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC pre-increment load instructions do not have side effectsHal Finkel2013-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178972 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC MCRF instruction does not have side effectsHal Finkel2013-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178971 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC FMR instruction does not have side effectsHal Finkel2013-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178970 91177308-0d34-0410-b5e6-96231b3b80d8
* DW_FORM_sec_offset should be a relocation on platforms that useEric Christopher2013-04-07
| | | | | | | | | a relocation across sections. Do this for DW_AT_stmt list in the skeleton CU and check the relocations in the debug_info section. Add a FIXME for multiple CUs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178969 91177308-0d34-0410-b5e6-96231b3b80d8
* [cmake] Avoid rel+asserts warnings when passing -UNDEBUGReid Kleckner2013-04-07
| | | | | | | MSVC 2012 gives warning D9025, "overriding /D NDEBUG with -UNDEBUG". Removing the original definition of NDEBUG silences this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178967 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement LowerReturn_64 for SPARC v9.Jakob Stoklund Olesen2013-04-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Integer return values are sign or zero extended by the callee, and structs up to 32 bytes in size can be returned in registers. The CC_Sparc64 CallingConv definition is shared between LowerFormalArguments_64 and LowerReturn_64. Function arguments and return values are passed in the same registers. The inreg flag is also used for return values. This is required to handle C functions returning structs containing floats and ints: struct ifp { int i; float f; }; struct ifp f(void); LLVM IR: define inreg { i32, float } @f() { ... ret { i32, float } %retval } The ABI requires that %retval.i is returned in the high bits of %i0 while %retval.f goes in %f1. Without the inreg return value attribute, %retval.i would go in %i0 and %retval.f would go in %f3 which is a more efficient way of returning %multiple values, but it is not ABI compliant for returning C structs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178966 91177308-0d34-0410-b5e6-96231b3b80d8
* SPARC v9 stack pointer bias.Jakob Stoklund Olesen2013-04-06
| | | | | | | | | | | 64-bit SPARC v9 processes use biased stack and frame pointers, so the current function's stack frame is located at %sp+BIAS .. %fp+BIAS where BIAS = 2047. This makes more local variables directly accessible via [%fp+simm13] addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178965 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement PPCInstrInfo::FoldImmediateHal Finkel2013-04-06
| | | | | | | | There are certain PPC instructions into which we can fold a zero immediate operand. We can detect such cases by looking at the register class required by the using operand (so long as it is not otherwise constrained). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178961 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC ISEL is a select and never has side effectsHal Finkel2013-04-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178960 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a comment to TargetInstrInfo about FoldImmediateHal Finkel2013-04-06
| | | | | | | This comment documents the current behavior of the ARM implementation of this callback, and also the soon-to-be-committed PPC version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178959 91177308-0d34-0410-b5e6-96231b3b80d8
* Complete formal arguments for the SPARC v9 64-bit ABI.Jakob Stoklund Olesen2013-04-06
| | | | | | | | | | | | | | | | | | | | | | | | All arguments are formally assigned to stack positions and then promoted to floating point and integer registers. Since there are more floating point registers than integer registers, this can cause situations where floating point arguments are assigned to registers after integer arguments that where assigned to the stack. Use the inreg flag to indicate 32-bit fragments of structs containing both float and int members. The three-way shadowing between stack, integer, and floating point registers requires custom argument lowering. The good news is that return values are passed in the exact same way, and we can share the code. Still missing: - Update LowerReturn to handle structs returned in registers. - LowerCall. - Variadic functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178958 91177308-0d34-0410-b5e6-96231b3b80d8
* typoNadav Rotem2013-04-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178949 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove last use of InMemoryStruct from MachOObjectFile.cpp.Rafael Espindola2013-04-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178948 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use InMemoryStruct<macho::SymtabLoadCommand>.Rafael Espindola2013-04-06
| | | | | | | This also required not using the RegisterStringTable API, which is also a good thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178947 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use InMemoryStruct in getSymbol64TableEntry.Rafael Espindola2013-04-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178946 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use InMemoryStruct in getSymbolTableEntry.Rafael Espindola2013-04-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178945 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use InMemoryStruct in getRelocation.Rafael Espindola2013-04-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178943 91177308-0d34-0410-b5e6-96231b3b80d8
* Dwarf: use utostr on CUID to append to SmallString.Manman Ren2013-04-06
| | | | | | | | | | We used to do "SmallString += CUID", which is incorrect, since CUID will be truncated to a char. rdar://problem/13573833 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178941 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed trailing whitespace.Michael Gottesman2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178932 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add support for buffer stores v2Tom Stellard2013-04-05
| | | | | | | | | v2: - Use the ADDR64 bit Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178931 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use same names for corresponding MUBUF operands and encoding fieldsTom Stellard2013-04-05
| | | | | | | | | | | | The code emitter knows how to encode operands whose name matches one of the encoding fields. If there is no match, the code emitter relies on the order of the operand and field definitions to determine how operands should be encoding. Matching by order makes it easy to accidentally break the instruction encodings, so we prefer to match by name. Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178930 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add RV670 processorTom Stellard2013-04-05
| | | | | | | | This is an R600 GPU with double support. Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178929 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add processor types for each SI variantTom Stellard2013-04-05
| | | | | | Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178928 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Avoid generating S_MOVs with 64-bit immediates v2Tom Stellard2013-04-05
| | | | | | | | | | | | | | SITargetLowering::analyzeImmediate() was converting the 64-bit values to 32-bit and then checking if they were an inline immediate. Some of these conversions caused this check to succeed and produced S_MOV instructions with 64-bit immediates, which are illegal. v2: - Clean up logic Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178927 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable early if conversion on PPCHal Finkel2013-04-05
| | | | | | | | | | | | | On cores for which we know the misprediction penalty, and we have the isel instruction, we can profitably perform early if conversion. This enables us to replace some small branch sequences with selects and avoid the potential stalls from mispredicting the branches. Enabling this feature required implementing canInsertSelect and insertSelect in PPCInstrInfo; isel code in PPCISelLowering was refactored to use these functions as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178926 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct the PPC A2 misprediction penaltyHal Finkel2013-04-05
| | | | | | | | The manual states that there is a minimum of 13 cycles from when the mispredicted branch is issued to when the correct branch target is issued. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178925 91177308-0d34-0410-b5e6-96231b3b80d8
* An objc_retain can serve as a use for a different pointer.Michael Gottesman2013-04-05
| | | | | | | This is the counterpart to commit r160637, except it performs the action in the bottomup portion of the data flow analysis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178922 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly model precise lifetime when given an incomplete dataflow sequence.Michael Gottesman2013-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The normal dataflow sequence in the ARC optimizer consists of the following states: Retain -> CanRelease -> Use -> Release The optimizer before this patch stored the uses that determine the lifetime of the retainable object pointer when it bottom up hits a retain or when top down it hits a release. This is correct for an imprecise lifetime scenario since what we are trying to do is remove retains/releases while making sure that no ``CanRelease'' (which is usually a call) deallocates the given pointer before we get to the ``Use'' (since that would cause a segfault). If we are considering the precise lifetime scenario though, this is not correct. In such a situation, we *DO* care about the previous sequence, but additionally, we wish to track the uses resulting from the following incomplete sequences: Retain -> CanRelease -> Release (TopDown) Retain <- Use <- Release (BottomUp) *NOTE* This patch looks large but the most of it consists of updating test cases. Additionally this fix exposed an additional bug. I removed the test case that expressed said bug and will recommit it with the fix in a little bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178921 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r178845 with fix - Fix bug in PEI's virtual-register scavengingHal Finkel2013-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes PEI as previously described, but correctly handles the case where the instruction defining the virtual register to be scavenged is the first in the block. Arnold provided me with a bugpoint-reduced test case, but even that seems too large to use as a regression test. If I'm successful in cleaning it up then I'll commit that as well. Original commit message: This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178919 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the target options specified on a function to reset the back-end.Bill Wendling2013-04-05
| | | | | | | | | During LTO, the target options on functions within the same Module may change. This would necessitate resetting some of the back-end. Do this for X86, because it's a Friday afternoon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178917 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r178845 - Fix bug in PEI's virtual-register scavengingHal Finkel2013-04-05
| | | | | | | | | | | | | | | | | | | | | | Reverting because this breaks one of the LTO builders. Original commit message: This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178916 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up a bit. No functional change.Jim Grosbach2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178915 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable the optimization about promoting vector-element-access with symbolic ↵Shuxin Yang2013-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | index. This optimization is unstable at this moment; it 1) block us on a very important application 2) PR15200 3) test6 and test7 in test/Transforms/ScalarRepl/dynamic-vector-gep.ll (the CHECK command compare the output against wrong result) I personally believe this optimization should not have any impact on the autovectorized code, as auto-vectorizer is supposed to put gather/scatter in a "right" way. Although in theory downstream optimizaters might reveal some gather/scatter optimization opportunities, the chance is quite slim. For the hand-crafted vectorizing code, in term of redundancy elimination, load-CSE, copy-propagation and DSE can collectively achieve the same result, but in much simpler way. On the other hand, these optimizers are able to improve the code in a incremental way; in contrast, SROA is sort of all-or-none approach. However, SROA might slighly win in stack size, as it tries to figure out a stretch of memory tightenly cover the area accessed by the dynamic index. rdar://13174884 PR15200 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178912 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] XFAIL test-interp-vec-loadstore.ll in an attempt to turn builderAkira Hatanaka2013-04-05
| | | | | | | | | | | llvm-mips-linux green. llvm-mips-linux runs on a big endian machine. This test passes if I change 'e' to 'E' in the target data layout string. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178910 91177308-0d34-0410-b5e6-96231b3b80d8
* <rdar://problem/13551789> Fix a race in the LockFileManager.Douglas Gregor2013-04-05
| | | | | | | | | It's possible for the lock file to disappear and the owning process to return before we're able to see the generated file. Spin for a little while to see if it shows up before failing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178909 91177308-0d34-0410-b5e6-96231b3b80d8
* <rdar://problem/13551789> Fix yet another race in unique_file.Douglas Gregor2013-04-05
| | | | | | | | | | | If the directory that will contain the unique file doesn't exist when we tried to create the file, but another process creates it before we get a chance to try creating it, we would bail out rather than try to create the unique file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178908 91177308-0d34-0410-b5e6-96231b3b80d8
* [Support][FileSystem] Fix identify_magic for big endian ELF.Michael J. Spencer2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178905 91177308-0d34-0410-b5e6-96231b3b80d8
* Move yaml2obj to tools too.Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178904 91177308-0d34-0410-b5e6-96231b3b80d8
* Define versions of Section that are explicitly marked as little endian.Rafael Espindola2013-04-05
| | | | | | These should really be templated like ELF, but this is a start. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178896 91177308-0d34-0410-b5e6-96231b3b80d8
* Added two debug logging messages to VisitInstructionsTopDown to match ↵Michael Gottesman2013-04-05
| | | | | | VisitInstructionsBottomUp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178895 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use InMemoryStruct in getSection and getSection64.Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178894 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleaned up whitespace and made debug logging less verbose.Michael Gottesman2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178893 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the test/CodeGen/X86/win32_sret.ll reliable on any CPU by explicitly ↵Timur Iskhodzhanov2013-04-05
| | | | | | specifying the -mcpu git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178885 91177308-0d34-0410-b5e6-96231b3b80d8
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