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* Atomics: make use of the "cmpxchg weak" instruction.Tim Northover2014-06-13
| | | | | | | | | This also simplifies the IR we create slightly: instead of working out where success & failure should go manually, it turns out we can just always jump to a success/failure block created for the purpose. Later phases will sort out the mess without much difficulty. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210917 91177308-0d34-0410-b5e6-96231b3b80d8
* Atomics: switch direction of cmpxchg comparisonTim Northover2014-06-13
| | | | | | | | This has two benefits: it makes the result more suitable for direct insertaion into the struct to emulate the new cmpxchg, and it means the name we give the instruction matches its actual effect better. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210916 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Remove AMDIL instruction and register definitionsTom Stellard2014-06-13
| | | | | | Most of these are no longer used any more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210915 91177308-0d34-0410-b5e6-96231b3b80d8
* opt: Initialize asm printersTobias Grosser2014-06-13
| | | | | | | | | | | | | | Without initializing the assembly printers a shared library build of opt is linked with these libraries whereas for a static build these libraries are dead code eliminated. This is unfortunate for plugins in case they want to use them, as they neither can rely on opt to provide this functionality nor can they link the printers in themselves as this breaks with a shared object build of opt. This patch calls InitializeAllAsmPrinters() from opt, which increases the static binary size from 50MB -> 52MB on my system (all backends compiled) and causes no measurable increase in the time needed to run 'make check'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210914 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused and odd code.Rafael Espindola2014-06-13
| | | | | | | | This code was never being used and any use of it would look fairly strange. For example, it would try to map a object_error::parse_failed to std::errc::invalid_argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210912 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove broken include.Rafael Espindola2014-06-13
| | | | | | Looks like I got some git merge wrong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210911 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix KillTheDoctor after r210725.Rafael Espindola2014-06-13
| | | | | | | We don't map these windows errors to generic ones since errc::timed_out is not defined on mingw. Just use the raw windows error value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210910 91177308-0d34-0410-b5e6-96231b3b80d8
* SCCP: update for cmpxchg returning { iN, i1 } now.Tim Northover2014-06-13
| | | | | | I accidentally missed this one since its use looked OK locally. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210909 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] Relocation R_MIPS_PC18_S3Zoran Jovanovic2014-06-13
| | | | | | | Differential Revision: http://reviews.llvm.org/D3890 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210908 91177308-0d34-0410-b5e6-96231b3b80d8
* Docs: remove extra {} around result types.Tim Northover2014-06-13
| | | | | | | | It makes the types look like they're single-element structures. And when we have instructions that *do* result in a struct, that can get confusing rather quickly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210905 91177308-0d34-0410-b5e6-96231b3b80d8
* Docs: fix grammar error in descriptionTim Northover2014-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210904 91177308-0d34-0410-b5e6-96231b3b80d8
* IR: add "cmpxchg weak" variant to support permitted failure.Tim Northover2014-06-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a weak variant of the cmpxchg operation, as described in C++11. A cmpxchg instruction with this modifier is permitted to fail to store, even if the comparison indicated it should. As a result, cmpxchg instructions must return a flag indicating success in addition to their original iN value loaded. Thus, for uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The second flag is 1 when the store succeeded. At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been added as the natural representation for the new cmpxchg instructions. It is a strong cmpxchg. By default this gets Expanded to the existing ATOMIC_CMP_SWAP during Legalization, so existing backends should see no change in behaviour. If they wish to deal with the enhanced node instead, they can call setOperationAction on it. Beware: as a node with 2 results, it cannot be selected from TableGen. Currently, no use is made of the extra information provided in this patch. Test updates are almost entirely adapting the input IR to the new scheme. Summary for out of tree users: ------------------------------ + Legacy Bitcode files are upgraded during read. + Legacy assembly IR files will be invalid. + Front-ends must adapt to different type for "cmpxchg". + Backends should be unaffected by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210903 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bad copy-and-paste from r210652. AVX512 masked leading zero intrinsics.Cameron McInally2014-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210901 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add cache and pref instructionsDaniel Sanders2014-06-13
| | | | | | | | | | | | | | | | | | | Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210900 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] bc1any[24] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-13
| | | | | | | | | | | | | | Summary: These MIPS-3D instructions have never been implemented in LLVM so we only add testcases. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4115 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210899 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal ↵Daniel Sanders2014-06-13
| | | | | | | | | | | | | | | | | | | | | | | | | | is a normal instruction Summary: b(ge|lt)zal have been removed in MIPS32r6/MIPS64r6. However, bal (an alias for 'bgezal $zero, $offset') still remains with the same encoding it had prior to MIPS32r6/MIPS64r6. Updated the MipsNaCLELFStreamer, and MipsLongBranch to correctly handle the MIPS32r6/MIPS64r6 BAL instruction in addition to the existing BAL_BR pseudo. No changes were required to the CodeGen test that looks for BAL (test/CodeGen/Mips/longbranch.ll) since the new instruction has the same syntax. Depends on D4113 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4114 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210898 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][mips64r6] daddi is not available on MIPS64r6Daniel Sanders2014-06-13
| | | | | | | | | | | | | | | | | | Summary: It's not emitted by the code generator so we only need assembler tests. Also added missing daddi aliases from dsub mnemonics, and removed a couple duplicate dsub tests. Depends on D4112 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4113 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210897 91177308-0d34-0410-b5e6-96231b3b80d8
* [Win32] Let utils/not aware of abort(), aka llvm_unreachable(), in msvcrt.NAKAMURA Takumi2014-06-13
| | | | | | | | It has exit code as 3. abort(), aka unreachable, may be handled as crash. FIXME: Could we move this into Win32/Program.inc? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210895 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86/fast-isel-args-fail2.ll: Don't expect to fail with ↵NAKAMURA Takumi2014-06-13
| | | | | | -Asserts. It might or might not crash. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210894 91177308-0d34-0410-b5e6-96231b3b80d8
* Add HasCDI predicate to AVX512 VPBROADCASTM*.Cameron McInally2014-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210892 91177308-0d34-0410-b5e6-96231b3b80d8
* CPP backend: set volatile property on atomic instructions.Tim Northover2014-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210890 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix fastcc calling convention for Thumb1Oliver Stannard2014-06-13
| | | | | | | | | | When targetting Thumb1 on a processor which has a VFP unit (which is not accessible from Thumb1), we were converting the fastcc calling convention to AAPCS-VFP, which is not possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210889 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Don't call setOperationAction with things that aren't opcodes.Matt Arsenault2014-06-13
| | | | | | | | | CondCode actions are set with setCondCodeAction. This should have been a harmless bug since the values seem to only collide only with nodes that don't need to be handled, and these are already correctly setup elsewhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210888 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix selection error on i64 rotl / rotr.Matt Arsenault2014-06-13
| | | | | | Evergreen is still broken due to missing shl_parts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210885 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the last uses of 'using std::error_code'Rafael Espindola2014-06-13
| | | | | | This finishes the transition to std::error_code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210877 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove 'using std::error_code' from tools.Rafael Espindola2014-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210876 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix build on windows.Rafael Espindola2014-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210873 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove 'using std::errro_code' from lib.Rafael Espindola2014-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210871 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Add support for cvttss2si/cvttsd2si intrinsics.Juergen Ributzka2014-06-13
| | | | | | | | This adds support for the cvttss2si/cvttsd2si intrinsics. Preceding insertelement instructions are folded into the conversion instruction (if possible). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210870 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210869 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Drop use of cached TargetMachine in R600InstrInfo.cppTom Stellard2014-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210868 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove all uses of 'using std::error_code' from headers.Rafael Espindola2014-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210866 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cppTom Stellard2014-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210865 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] - Add branch weightsJuergen Ributzka2014-06-13
| | | | | | | Add branch weights to branch instructions, so that the following passes can optimize based on it (i.e. basic block ordering). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210863 91177308-0d34-0410-b5e6-96231b3b80d8
* Move ARMSelectionDAGInfo from the TargetMachine to the subtarget.Eric Christopher2014-06-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210862 91177308-0d34-0410-b5e6-96231b3b80d8
* Move to a private function to initialize subtarget dependenciesEric Christopher2014-06-13
| | | | | | | | so we can use initializer lists for the ARMSubtarget and then use this to initialize a moved DataLayout on the subtarget from the TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210861 91177308-0d34-0410-b5e6-96231b3b80d8
* [DWARF parser] Fix broken address ranges construction.Alexey Samsonov2014-06-12
| | | | | | | | | | | | | | | | | | Previous algorithm for constructing [Address ranges]->[Compile Units] mapping was wrong. It somewhat relied on the assumption that address ranges for different compile units may not overlap. It is not so. For example, two compile units may contain the definition of the same linkonce_odr function. These definitions will be merged at link-time, resulting in equivalent .debug_ranges entries for both these units Instead of sorting and merging original address ranges (from .debug_ranges and .debug_aranges), implement a different approach: save endpoints of all ranges, and then use a sweep-line approach to construct the desired mapping. If we find that certain address maps to several compilation units, we just pick any of them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210860 91177308-0d34-0410-b5e6-96231b3b80d8
* Have ARMSelectionDAGInfo take a DataLayout as it's argument as theEric Christopher2014-06-12
| | | | | | | DAG has access to the subtarget and TargetSelectionDAGInfo only needs a DataLayout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210859 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Add MachineMemOperand to load/store instructions.Juergen Ributzka2014-06-12
| | | | | | | | This commit adds MachineMemOperands to load and store instructions. This allows the peephole optimizer to fold load instructions. Unfortunatelly the peephole optimizer currently doesn't run at -O0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210858 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the PPCSelectionDAGInfo off the TargetMachine and onto theEric Christopher2014-06-12
| | | | | | subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210854 91177308-0d34-0410-b5e6-96231b3b80d8
* Make PPCSelectionDAGInfo take a DataLayout instead of a TargetMachineEric Christopher2014-06-12
| | | | | | since that's all it needs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210853 91177308-0d34-0410-b5e6-96231b3b80d8
* Move PPCTargetLowering off of the TargetMachine and onto the subtarget.Eric Christopher2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210852 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an extraneous this-> to access the subtarget.Eric Christopher2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210849 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename PPCSubTarget to Subtarget in PPCTargetLowering for consistency.Eric Christopher2014-06-12
| | | | | | Also remove an extra local subtarget in the initialization functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210848 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the scheduler's MaxObservedStall computation.Andrew Trick2014-06-12
| | | | | | | WenHan Gu pointed out this bug that results in an assert not being effective in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210846 91177308-0d34-0410-b5e6-96231b3b80d8
* Move PPCJITInfo off of the TargetMachine and onto the subtarget.Eric Christopher2014-06-12
| | | | | | | Needed to migrate a few functions around to avoid circular header dependencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210845 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the use of TargetMachine from PPCJITInfo and replace withEric Christopher2014-06-12
| | | | | | | the subtarget. Also remove unnecessary argument to the constructor at the same time, we already have access via the subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210844 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the build of KillTheDoctor.Rafael Espindola2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210843 91177308-0d34-0410-b5e6-96231b3b80d8
* [modules] The LLVM C API does not require C++!Richard Smith2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210842 91177308-0d34-0410-b5e6-96231b3b80d8
* Move PPCInstrInfo off of the target machine and onto the subtarget.Eric Christopher2014-06-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210839 91177308-0d34-0410-b5e6-96231b3b80d8
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