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* Move yaml2obj to tools too.Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178904 91177308-0d34-0410-b5e6-96231b3b80d8
* Define versions of Section that are explicitly marked as little endian.Rafael Espindola2013-04-05
| | | | | | These should really be templated like ELF, but this is a start. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178896 91177308-0d34-0410-b5e6-96231b3b80d8
* Added two debug logging messages to VisitInstructionsTopDown to match ↵Michael Gottesman2013-04-05
| | | | | | VisitInstructionsBottomUp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178895 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use InMemoryStruct in getSection and getSection64.Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178894 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleaned up whitespace and made debug logging less verbose.Michael Gottesman2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178893 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the test/CodeGen/X86/win32_sret.ll reliable on any CPU by explicitly ↵Timur Iskhodzhanov2013-04-05
| | | | | | specifying the -mcpu git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178885 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverting 178851 as it broke buildbotsRenato Golin2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178883 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add support for numeric displacement expressions in bracketedChad Rosier2013-04-05
| | | | | | | | | | | | | | | | | | | | | | | memory operands. Essentially, this layers an infix calculator on top of the parsing state machine. The scale on the index register is still expected to be an immediate __asm mov eax, [eax + ebx*4] and will not work with more complex expressions. For example, __asm mov eax, [eax + ebx*(2*2)] The plus and minus binary operators assume the numeric value of a register is zero so as to not change the displacement. Register operands should never be an operand for a multiply or divide operation; the scale*indexreg expression is always replaced with a zero on the operand stack to prevent such a case. rdar://13521380 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178881 91177308-0d34-0410-b5e6-96231b3b80d8
* [Support] Disable assertion dialogs from the MSVC debug CRTReid Kleckner2013-04-05
| | | | | | | | | | | | | | | | Summary: Sets a report hook that emulates pressing "retry" in the "abort, retry, ignore" dialog box that _CrtDbgReport normally raises. There are many other ways to disable assertion reports, but this was the only way I could find that still calls our exception handler. Reviewers: Bigcheese CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D625 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178880 91177308-0d34-0410-b5e6-96231b3b80d8
* Use ScalarBitSetTraits.Rafael Espindola2013-04-05
| | | | | | What was missing was were the type strong operator|. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178879 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix include guards to match new location.Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178877 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't fetch pointers from a InMemoryStruct.Rafael Espindola2013-04-05
| | | | | | | | InMemoryStruct is extremely dangerous as it returns data from an internal buffer when the endiannes doesn't match. This should fix the tests on big endian hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178875 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable JIT/MCJIT unit tests for targets with JIT support.Jyotsna Verma2013-04-05
| | | | | | | | | | | Change unittests/ExecutionEngine/Makefile to include Makefile.config before TARGET_HAS_JIT flag is checked. Fixes bug: http://llvm.org/bugs/show_bug.cgi?id=15669 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178871 91177308-0d34-0410-b5e6-96231b3b80d8
* Respect Addend when processing MCJIT relocations to local/global symbols.Ulrich Weigand2013-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the RuntimeDyldELF::processRelocationRef routine finds the target symbol of a relocation in the local or global symbol table, it performs a section-relative relocation: Value.SectionID = lsi->second.first; Value.Addend = lsi->second.second; At this point, however, any Addend that might have been specified in the original relocation record is lost. This is somewhat difficult to trigger for relocations within the code section since they usually do not contain non-zero Addends (when built with the default JIT code model, in any case). However, the problem can be reliably triggered by a relocation within the data section caused by code like: int test[2] = { -1, 0 }; int *p = &test[1]; The initializer of "p" will need a relocation to "test + 4". On platforms using RelA relocations this means an Addend of 4 is required. Current code ignores this addend when processing the relocation, resulting in incorrect execution. Fixed by taking the Addend into account when processing relocations to symbols found in the local or global symbol table. Tested on x86_64-linux and powerpc64-linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178869 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-symbolizer: correctly parse filenames given in quotesAlexey Samsonov2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178859 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a basic test for llvm-symbolizer toolAlexey Samsonov2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178858 91177308-0d34-0410-b5e6-96231b3b80d8
* Buildbot fix for r178851: mistake was in wrong ↵Stepan Dyatkovskiy2013-04-05
| | | | | | TargetRegisterInfo::getRegClass usage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178854 91177308-0d34-0410-b5e6-96231b3b80d8
* Add obj2yaml to test dependenciesAlexey Samsonov2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178852 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR14824: "Optimization arm_ldst_opt inserts newly generated ↵Stepan Dyatkovskiy2013-04-05
| | | | | | | | | | | | | | | | | | | instruction vldmia at incorrect position". Patch introduces memory operands tracking in ARMLoadStoreOpt::LoadStoreMultipleOpti. For each register it keeps the order of load operations as it was before optimization pass. It is kind of deep improvement of fix proposed by Hao: http://llvm.org/bugs/show_bug.cgi?id=14824#c4 But it also tracks conflicts between different register classes (e.g. D2 and S5). For more details see: Bug description: http://llvm.org/bugs/show_bug.cgi?id=14824 LLVM Commits discussion: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130311/167936.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130318/168688.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130325/169376.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130401/170238.html git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178851 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a SchedMachineModel for the PPC G5Hal Finkel2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178850 91177308-0d34-0410-b5e6-96231b3b80d8
* The ppc bots say this is the last broken line, so lets try one more :-(Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178849 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a SchedMachineModel for the PPC A2Hal Finkel2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178848 91177308-0d34-0410-b5e6-96231b3b80d8
* One more try before I just delete the macho bits until tomorrow.Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178847 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in PEI's virtual-register scavengingHal Finkel2013-04-05
| | | | | | | | | | | | | | | | | | | | This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178845 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM scheduler model: Add scheduler info to more instructions and resourceArnold Schwaighofer2013-04-05
| | | | | | descriptions for compares git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178844 91177308-0d34-0410-b5e6-96231b3b80d8
* More test loosening.Rafael Espindola2013-04-05
| | | | | | Sorry for so many commits, but llvm is still building on my ppc vm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178843 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM scheduler model: Swift has varying latencies, uops for simple ALU opsArnold Schwaighofer2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178842 91177308-0d34-0410-b5e6-96231b3b80d8
* Loosen this test too.Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178841 91177308-0d34-0410-b5e6-96231b3b80d8
* Loosen this test.Rafael Espindola2013-04-05
| | | | | | | | | Looks like there is a big endian/little endian problem here. Loosen the test to try to get the bots green while llvm builds on a ppc qemu vm. The failure was in http://lab.llvm.org:8011/builders/clang-ppc64-elf-linux2/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178839 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove empty directory.Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178837 91177308-0d34-0410-b5e6-96231b3b80d8
* Move obj2yaml to tools to sort out make's dependencies.Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178835 91177308-0d34-0410-b5e6-96231b3b80d8
* Build obj2yaml with configure+make.Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178833 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test for obj2yaml in preparation for refactoring it.Rafael Espindola2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178829 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up some confusing language, and use more realistic examples.Jakob Stoklund Olesen2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178828 91177308-0d34-0410-b5e6-96231b3b80d8
* RegisterPressure heuristics currently require signed comparisons.Andrew Trick2013-04-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178823 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable DFSResult for ConvergingScheduler.Andrew Trick2013-04-05
| | | | | | | | For now, just save the compile time since the ConvergingScheduler heuristics don't use this analysis. We'll probably enable it later after compile-time investigation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178822 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineScheduler: format DEBUG output.Andrew Trick2013-04-05
| | | | | | | I'm getting more serious about tuning and enabling on x86/ARM. Start by making the trace readable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178821 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorizer: Pass OperandValueKind information to the cost modelArnold Schwaighofer2013-04-04
| | | | | | | | | | | | Pass down the fact that an operand is going to be a vector of constants. This should bring the performance of MultiSource/Benchmarks/PAQ8p/paq8p on x86 back. It had degraded to scalar performance due to my pervious shift cost change that made all shifts expensive on x86. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178809 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 cost model: Differentiate cost for vector shifts of constantsArnold Schwaighofer2013-04-04
| | | | | | | | | | | | SSE2 has efficient support for shifts by a scalar. My previous change of making shifts expensive did not take this into account marking all shifts as expensive. This would prevent vectorization from happening where it is actually beneficial. With this change we differentiate between shifts of constants and other shifts. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178808 91177308-0d34-0410-b5e6-96231b3b80d8
* CostModel: Add parameter to instruction cost to further classify operand valuesArnold Schwaighofer2013-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On certain architectures we can support efficient vectorized version of instructions if the operand value is uniform (splat) or a constant scalar. An example of this is a vector shift on x86. We can efficiently support for (i = 0 ; i < ; i += 4) w[0:3] = v[0:3] << <2, 2, 2, 2> but not for (i = 0; i < ; i += 4) w[0:3] = v[0:3] << x[0:3] This patch adds a parameter to getArithmeticInstrCost to further qualify operand values as uniform or uniform constant. Targets can then choose to return a different cost for instructions with such operand values. A follow-up commit will test this feature on x86. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178807 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: revert 178722 for now.Manman Ren2013-04-04
| | | | | | | | | | | | | | There is a difference for FORM_ref_addr between DWARF 2 and DWARF 3+. Since Eric is against guarding DWARF 2 ref_addr with DarwinGDBCompat, we are still in discussion on how to handle this. The correct solution is to update our header to say version 4 instead of version 2 and update tool chains as well. rdar://problem/13559431 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178806 91177308-0d34-0410-b5e6-96231b3b80d8
* typoAdrian Prantl2013-04-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178804 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the current PPC BCL definition to BCLalwaysHal Finkel2013-04-04
| | | | | | | | | | | | BCL is normally a conditional branch-and-link instruction, but has an unconditional form (which is used in the SjLj code, for example). To make clear that this BCL instruction definition is specifically the special unconditional form (which does not meaningfully take a condition-register input), rename it to BCLalways. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178803 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Improve code generation for mixed-precision reciprocal sqrtHal Finkel2013-04-04
| | | | | | | | The DAGCombine logic that recognized a/sqrt(b) and transformed it into a multiplication by the reciprocal sqrt did not handle cases where the sqrt and the division were separated by an fpext or fptrunc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178801 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Expand br_cc.Jyotsna Verma2013-04-04
| | | | | | | | | | | | | | | It fixes following tests for Hexagon: CodeGen/Generic/2003-07-29-BadConstSbyte.ll CodeGen/Generic/2005-10-21-longlonggtu.ll CodeGen/Generic/2009-04-28-i128-cmp-crash.ll CodeGen/Generic/MachineBranchProb.ll CodeGen/Generic/builtin-expect.ll CodeGen/Generic/pr12507.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178794 91177308-0d34-0410-b5e6-96231b3b80d8
* Reassociate: Avoid iterator invalidation.Benjamin Kramer2013-04-04
| | | | | | | | OpndPtrs stored pointers into the Opnd vector that became invalid when the vector grows. Store indices instead. Sadly I only have a large testcase that only triggers under valgrind, so I didn't include it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178793 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable 2010-10-01-crash.ll for Hexagon as the Hexagon frontend willJyotsna Verma2013-04-04
| | | | | | | | never produce a byval parameter with size < 8 bytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178792 91177308-0d34-0410-b5e6-96231b3b80d8
* Add back parsing of header charactestics.Rafael Espindola2013-04-04
| | | | | | | | It had been dropped during the switch to yaml::IO. Also add a test going from yaml2obj to llvm-readobj. It can be extended as we add more fields/formats to yaml2obj. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178786 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add bru instruction.Richard Osborne2013-04-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] The RRegs register class is a superset of GRRegs.Richard Osborne2013-04-04
| | | | | | | | | | At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
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