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* Code cleanup.Logan Chien2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211697 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Polly to the ignored trees.Chandler Carruth2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211695 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Add intrinsics for the pshufd, pshuflw, and pshufhw instructions.Chandler Carruth2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211694 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply r211399, "Generate native unwind info on Win64" with a fix to ↵NAKAMURA Takumi2014-06-25
| | | | | | | | | | | | | | | | | | | | | | | ignore SEH pseudo ops in X86 JIT emitter. -- This patch enables LLVM to emit Win64-native unwind info rather than DWARF CFI. It handles all corner cases (I hope), including stack realignment. Because the unwind info is not flexible enough to describe stack frames with a gap of unknown size in the middle, such as the one caused by stack realignment, I modified register spilling code to place all spills into the fixed frame slots, so that they can be accessed relative to the frame pointer. Patch by Vadim Chugunov! Reviewed By: rnk Differential Revision: http://reviews.llvm.org/D4081 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211691 91177308-0d34-0410-b5e6-96231b3b80d8
* Reformat.NAKAMURA Takumi2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211689 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Add target combine rule to select ADDSUB instructions from a build_vectorAndrea Di Biagio2014-06-25
| | | | | | | | | | | | | | | | | | | This patch teaches the backend how to combine a build_vector that implements an 'addsub' between packed float vectors into a sequence of vector add and vector sub followed by a VSELECT. The new VSELECT is expected to be lowered into a BLENDI. At ISel stage, the sequence 'vector add + vector sub + BLENDI' is pattern-matched against ISel patterns added at r211427 to select 'addsub' instructions. Added three more ISel patterns for ADDSUB. Added test sse3-avx-addsub-2.ll to verify that we correctly emit 'addsub' instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211679 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor out part of LICM::sink into a helper function.Evgeniy Stepanov2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211678 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix unresolved symbols when loading gold pluginAlexey Volkov2014-06-25
| | | | | | | Differential Revision: http://reviews.llvm.org/D4275 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211675 91177308-0d34-0410-b5e6-96231b3b80d8
* [LICM] Don't create more than one copy of an instruction per loop exit block ↵Evgeniy Stepanov2014-06-25
| | | | | | | | | | | | | | | | | | | | | when sinking. Fixes exponential compilation complexity in PR19835, caused by LICM::sink not handling the following pattern well: f = op g e = op f, g d = op e c = op d, e b = op c a = op b, c When an instruction with N uses is sunk, each of its operands gets N new uses (all of them - phi nodes). In the example above, if a had 1 use, c would have 2, e would have 4, and g would have 8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211673 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix another asserting method in the null streamer.Rafael Espindola2014-06-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211668 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a regression from r211653.Rafael Espindola2014-06-25
| | | | | | | The method was empty in the null streamer but I mistakenly replaced it with the aborting one in MCStreamer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211666 91177308-0d34-0410-b5e6-96231b3b80d8
* MCNullStreamer.cpp: Roll back a few empty methods that have been marked as ↵NAKAMURA Takumi2014-06-25
| | | | | | | | | | | unreachable in MCStreamer.cpp. void EmitCOFFSecRel32(MCSymbol const *Symbol) override {} void EmitGPRel32Value(const MCExpr *Value) override {} It should fix crash like "llc -mtriple=i686-cygwin -filetype=null". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211664 91177308-0d34-0410-b5e6-96231b3b80d8
* CodeGen/X86/pr20088.ll: Add -march=x86-64, or llc fails due to non-x86 ↵NAKAMURA Takumi2014-06-25
| | | | | | default target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211659 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SourceMgr::getMemoryBuffer() in a couple of placesAlp Toker2014-06-25
| | | | | | Cleanup only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211656 91177308-0d34-0410-b5e6-96231b3b80d8
* Move some trivial methods up to MCStreamer.Rafael Espindola2014-06-25
| | | | | | This saves some duplicated boilerplate in RecordStreamer and NullStreamer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211653 91177308-0d34-0410-b5e6-96231b3b80d8
* [RuntimeDyld] Adds the necessary hooks to MCJIT to be able to debug generatedLang Hames2014-06-25
| | | | | | | | | | MachO files using the GDB JIT debugging interface. Patch by Keno Fischer. Thanks Keno! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211652 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify the handling of .cfi_endproc.Rafael Espindola2014-06-25
| | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211651 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify EmitLabel.Rafael Espindola2014-06-24
| | | | | | | All the "real" streamers were already calling to MCStreamer::EmitLabel to do part of the work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211646 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Fold XALU condition into branch and compare.Juergen Ributzka2014-06-24
| | | | | | | Optimize the codegen of select and branch instructions to directly use the EFLAGS from the {s|u}{add|sub|mul}.with.overflow intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211645 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use a ComplexPattern for MUBUF storesTom Stellard2014-06-24
| | | | | | | | Now that non-leaf ComplexPatterns are allowed we can fold all the MUBUF store patterns into the instruction definition. We will also be able to reuse this new ComplexPattern for MUBUF loads and atomic operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211644 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Promote i64 stores to v2i32Tom Stellard2014-06-24
| | | | | | Now we need only one 64-bit pattern for stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211643 91177308-0d34-0410-b5e6-96231b3b80d8
* ldr-pseudo-obj-errors.s: Fix silly copypasto.NAKAMURA Takumi2014-06-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211642 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/MC/AArch64/ldr-pseudo-obj-errors.s: Add -triple=aarch64-linux. ↵NAKAMURA Takumi2014-06-24
| | | | | | | | AArch64 is unaware of PECOFF for now. FIXME: This should pass for also targeting aarch64-darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211640 91177308-0d34-0410-b5e6-96231b3b80d8
* Print a=b as an assignment.Rafael Espindola2014-06-24
| | | | | | | | | | | In assembly the expression a=b is parsed as an assignment, so it should be printed as one. This remove a truly horrible hack for producing a label with "a=.". It would be used by codegen but would never be reached by the asm parser. Sorry I missed this when it was first committed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211639 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix inconsistency in rsq instructions.Matt Arsenault2014-06-24
| | | | | | | | | | | | | R600 was using a clamped version of rsq, but SI was not. Add a new rsq_clamped intrinsic and use them consistently. It's unclear to me from the documentation what behavior the R600 instructions have, so I assume they have the legacy behavior described by the SI documents. For R600, use RECIPSQRT_IEEE for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also has RECIPSQRT_FF, which I'm not sure how it fits in here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211637 91177308-0d34-0410-b5e6-96231b3b80d8
* fixed a few typos in commentsSanjay Patel2014-06-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211634 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up scoping in a few tests (and delete one that validates unnecessary ↵David Blaikie2014-06-24
| | | | | | | | | | | | | | | | behavior). Most of this is just tests that were silently succeeding in spite of schema changes I made over a year ago. Cleaning them up as they lead to failures in a change I'm working on/will come soon. test/DebugInfo/2010-01-19-DbgScope.ll was removed as it tested miscoping where a DebugLoc described a location not in the current function. The test case doesn't describe why this is a valid situation and should be supported, so I'm removing it and shortly going to commit changes that make this firmly unsupported/assert-fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211628 91177308-0d34-0410-b5e6-96231b3b80d8
* [PPC64] Fix PR20071 (fctiduz generated for targets lacking that instruction)Bill Schmidt2014-06-24
| | | | | | | | | | | | | | | | | | PR20071 identifies a problem in PowerPC's fast-isel implementation for floating-point conversion to integer. The fctiduz instruction was added in Power ISA 2.06 (i.e., Power7 and later). However, this instruction is being generated regardless of which 64-bit PowerPC target is selected. The intent is for fast-isel to punt to DAG selection when this instruction is not available. This patch implements that change. For testing purposes, the existing fast-isel-conversion.ll test adds a RUN line for -mcpu=970 and tests for the expected code generation. Additionally, the existing test fast-isel-conversion-p5.ll was found to be incorrectly expecting the unavailable instruction to be generated. I've removed these test variants since we have adequate coverage in fast-isel-conversion.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211627 91177308-0d34-0410-b5e6-96231b3b80d8
* vpblend intrinsics combines as shifts intrinsics due to absence return stmt ↵Robert Khasanov2014-06-24
| | | | | | | | | | | between them Fix PR20088 Differential Revision: http://reviews.llvm.org/D4277 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211617 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Remove DIV_INFMatt Arsenault2014-06-24
| | | | | | | This corresponded to an amdil instruction which there is a 2 instruction equivalent for. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211616 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Move pattern to instruction definitionMatt Arsenault2014-06-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211614 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test case in r211605/r211533Weiming Zhao2014-06-24
| | | | | | | | | The test case in "Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64" should only work with Linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211613 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new debug kind LocTrackingOnly.Diego Novillo2014-06-24
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This new debug emission kind supports emitting line location information in all instructions, but stops code generation from emitting debug info to the final output. This mode is useful when the backend wants to track source locations during code generation, but it does not want to produce debug info. This is currently used by optimization remarks (-pass-remarks, -pass-remarks-missed and -pass-remarks-analysis). To prevent debug info emission, DIBuilder never inserts the annotation 'llvm.dbg.cu' when LocTrackingOnly is enabled. Reviewers: echristo, dblaikie Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D4234 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211609 91177308-0d34-0410-b5e6-96231b3b80d8
* Resubmit commit r211533Weiming Zhao2014-06-24
| | | | | | | | | "Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64" Missed files are added in this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211605 91177308-0d34-0410-b5e6-96231b3b80d8
* CodeGen: Avoid multiple strlen callsDavid Majnemer2014-06-24
| | | | | | | Use a StringRef to hold our section prefix. This avoids multiple calls to strlen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211602 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix TPsoft for Thumb modeChristian Pirker2014-06-24
| | | | | | | | Reviewed at http://reviews.llvm.org/D4230 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211601 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an empty directory left after r211508.Alexander Kornienko2014-06-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211600 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace two release calls with std::move. I missed this on the previous commit.Rafael Espindola2014-06-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211597 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass a unique_ptr<MemoryBuffer> to the constructors in the Binary hierarchy.Rafael Espindola2014-06-24
| | | | | | | Once the objects are constructed, they own the buffer. Passing a unique_ptr makes that clear. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211595 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert: r211588 - [mips] Use __clear_cache builtin instead of cacheflush() ↵Daniel Sanders2014-06-24
| | | | | | | | | | | | | in Unix Memory::InvalidateInstructionCache() Buildbot reports a test failure on the llvm-mips-linux builder and blames r211588. Although it doesn't appear in the blamelist, it seems it could also be r211587 (because it's committed to compiler-rt?) since they were tested together. Reverting the most likely suspect (r211588) to confirm one way or the other. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211594 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r211287, "Remove support for LLVM runtime multi-threading."NAKAMURA Takumi2014-06-24
| | | | | | libclang still requires it on cygming, lack of incomplete <mutex>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211592 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Added support for assembling sdbbp.Daniel Sanders2014-06-24
| | | | | | | | | | | Summary: This instruction is re-encoded in MIPS32r6/MIPS64r6 without changing the restrictions. We hadn't implemented it for earlier ISA's so it has been added to those too. Differential Revision: http://reviews.llvm.org/D4265 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211590 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use __clear_cache builtin instead of cacheflush() in Unix ↵Daniel Sanders2014-06-24
| | | | | | | | | | | | Memory::InvalidateInstructionCache() MIPS64 Android bionic has removed cacheflush(). Use __clear_cache() instead for 32-bit and 64-bit MIPS Patch by Duane Sand <Duane.Sand@imgtec.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211588 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Disable umul.with.overflow recognition for vectors.Benjamin Kramer2014-06-24
| | | | | | It doesn't make a lot on most targets and the code isn't ready for it. PR20113. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211583 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Don't try to reorder shuffles where the mask is a ConstantExpr.Benjamin Kramer2014-06-24
| | | | | | We can't analyze the individual values of a vector expression. PR20114. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211581 91177308-0d34-0410-b5e6-96231b3b80d8
* GlobalOpt: Don't optimize dllimport for initializersDavid Majnemer2014-06-24
| | | | | | | | | Referencing a dllimport variable requires actually instructions, not just a relocation. This fixes PR19955. Differential Revision: http://reviews.llvm.org/D4249 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211571 91177308-0d34-0410-b5e6-96231b3b80d8
* Include <tuple> for std::tieAlexey Samsonov2014-06-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211569 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Fix a build_vector pattern match failKevin Qin2014-06-24
| | | | | | caused by defect in isBuildVectorAllZeros(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211567 91177308-0d34-0410-b5e6-96231b3b80d8
* [Disasm][AVX512] Implement decoding of top bit for non-destructive reg fieldsAdam Nemet2014-06-24
| | | | | | | | | V' bit in the P2 byte of the EVEX prefix provides the top bit of the NDD and NDS register fields. This was simply not used in the decoder until now. Fixes <rdar://problem/17402661> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211565 91177308-0d34-0410-b5e6-96231b3b80d8
* [Emacs] Use spaces rather than tabs for indentation in tablegen-modeAdam Nemet2014-06-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211564 91177308-0d34-0410-b5e6-96231b3b80d8
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