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* r182085 introduced a change that triggered an assertion on ARM. This is an ↵David Tweed2013-05-17
| | | | | | | | | immediate fix which doesn't resolve the deeper problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182098 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Fix hi/lo encoding in old-style code emitterUlrich Weigand2013-05-17
| | | | | | | | | | | | | | | | | | | This patch implements the equivalent change to r182091/r182092 in the old-style code emitter. Instead of having two separate 16-bit immediate encoding routines depending on the instruction, this patch introduces a single encoder that checks the machine operand flags to decide whether the low or high half of a symbol address is required. Since now both encoders make no further distinction between "symbolLo" and "symbolHi", the .td operand can now use a single getS16ImmEncoding method. Tested by running the old-style JIT tests on 32-bit Linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182097 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Merge/rename PPC fixup typesUlrich Weigand2013-05-17
| | | | | | | | | | | | | | | | Now that fixup_ppc_ha16 and fixup_ppc_lo16 are being treated exactly the same everywhere, it no longer makes sense to have two fixup types. This patch merges them both into a single type fixup_ppc_half16, and renames fixup_ppc_lo16_ds to fixup_ppc_half16ds for consistency. (The half16 and half16ds names are taken from the description of relocation types in the PowerPC ABI.) No change in code generation expected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182092 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Fix processing of ha16/lo16 fixupsUlrich Weigand2013-05-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current PowerPC MC back end distinguishes between fixup_ppc_ha16 and fixup_ppc_lo16, which are determined by the instruction the fixup applies to, and uses this distinction to decide whether a fixup ought to resolve to the high or the low part of a symbol address. This isn't quite correct, however. It is valid -if unusual- assembler to use, e.g. li 1, symbol@ha or lis 1, symbol@l Whether the high or the low part of the address is used depends solely on the @ suffix, not on the instruction. In addition, both li 1, symbol and lis 1, symbol are valid, assuming the symbol address fits into 16 bits; again, both will then refer to the actual symbol value (so li will load the value itself, while lis will load the value shifted by 16). To fix this, two places need to be adapted. If the fixup cannot be resolved at assembler time, a relocation needs to be emitted via PPCELFObjectWriter::getRelocType. This routine already looks at the VK_ type to determine the relocation. The only problem is that will reject any _LO modifier in a ha16 fixup and vice versa. This is simply incorrect; any of those modifiers ought to be accepted for either fixup type. If the fixup *can* be resolved at assembler time, adjustFixupValue currently selects the high bits of the symbol value if the fixup type is ha16. Again, this is incorrect; see the above example lis 1, symbol Now, in theory we'd have to respect a VK_ modifier here. However, in fact common code never even attempts to resolve symbol references using any nontrivial VK_ modifier at assembler time; it will always fall back to emitting a reloc and letting the linker handle it. If this ever changes, presumably there'd have to be a target callback to resolve VK_ modifiers. We'd then have to handle @ha etc. there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182091 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo (ouput => output)Sylvestre Ledru2013-05-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182090 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't cast away constness.Benjamin Kramer2013-05-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182086 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor changes to the MCJITTest unittests to use the correct API for finalizingDavid Tweed2013-05-17
| | | | | | | | the JIT object (including XFAIL an ARM test that now needs fixing). Also renames internal function for consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182085 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: return undef instead of null for skipped argumentsChristian Konig2013-05-17
| | | | | | | | | | | | This is a candidate for the stable branch. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=64694 Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182084 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Prevent instructions that defines or uses %o7 to be in call's delay ↵Venkatraman Govindaraju2013-05-16
| | | | | | slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182063 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate debug info for by-value struct args even if they are not used.Adrian Prantl2013-05-16
| | | | | | radar://problem/13865940 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182062 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-objdump: Initialize MCDisassembler once instead of for each section.Ahmed Bougacha2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182054 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Improve instruction selection for pattern (store (fp_to_sint $src), ↵Akira Hatanaka2013-05-16
| | | | | | | | | | | | | | | | | | $ptr). Previously, three instructions were needed: trunc.w.s $f0, $f2 mfc1 $4, $f0 sw $4, 0($2) Now we need only two: trunc.w.s $f0, $f2 swc1 $f0, 0($2) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182053 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove addFrameMove.Rafael Espindola2013-05-16
| | | | | | | Now that we have good testing, remove addFrameMove and create cfi instructions directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182052 91177308-0d34-0410-b5e6-96231b3b80d8
* More test coverage for addFrameMove.Rafael Espindola2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182051 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Factor out unaligned store lowering code.Akira Hatanaka2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182050 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix cpu on test CodeGen/PowerPC/ctrloop-fp64.llHal Finkel2013-05-16
| | | | | | We need ppc instead of generic to override native features on ppc machines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182049 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips assembler: Add TwoOperandConstraint definitionsJack Carter2013-05-16
| | | | | | | | | | | | | | | | This patch removes alias definition for addiu $rs,$imm and instead uses the TwoOperandAliasConstraint field in the ArithLogicI instruction class. This way all instructions that inherit ArithLogicI class have the same macro defined. The usage examples are added to test files. Patch by Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182048 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips td file formatting: white space and long linesJack Carter2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182047 91177308-0d34-0410-b5e6-96231b3b80d8
* More addFrameMove test coverage.Rafael Espindola2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182046 91177308-0d34-0410-b5e6-96231b3b80d8
* Create an new preheader in PPCCTRLoops to avoid counter register clobbersHal Finkel2013-05-16
| | | | | | | | | | | | | Some IR-level instructions (such as FP <-> i64 conversions) are not chained w.r.t. the mtctr intrinsic and yet may become function calls that clobber the counter register. At the selection-DAG level, these might be reordered with the mtctr intrinsic causing miscompiles. To avoid this situation, if an existing preheader has instructions that might use the counter register, create a new preheader for the mtctr intrinsic. This extra block will be remerged with the old preheader at the MI level, but will prevent unwanted reordering at the selection-DAG level. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182045 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Test case for r182042. Add comment.Akira Hatanaka2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182044 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix instruction selection pattern for sint_to_fp node to avoid ↵Akira Hatanaka2013-05-16
| | | | | | | | | | | | | | | | | | | | emitting an invalid instruction sequence. Rather than emitting an int-to-FP move instruction and an int-to-FP conversion instruction during instruction selection, we emit a pseudo instruction which gets expanded post-RA. Without this change, register allocation can possibly insert a floating point register move instruction between the two instructions, which is not valid according to the ISA manual. mtc1 $f4, $4 # int-to-fp move instruction. mov.s $f2, $f4 # move contents of $f4 to $f2. cvt.s.w $f0, $f2 # int-to-fp conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182042 91177308-0d34-0410-b5e6-96231b3b80d8
* More test coverage for addFrameMove.Rafael Espindola2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182041 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips assembler: Add branch macro definitionsJack Carter2013-05-16
| | | | | | | | | | | | | This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows: bnez $rs,$imm => bne $rs,$zero,$imm beqz $rs,$imm => beq $rs,$zero,$imm The corresponding test cases are added. Patch by Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombine: Also shrink eq compares where the constant is exactly as large ↵Benjamin Kramer2013-05-16
| | | | | | | | | | | | | as the smaller type. if ((x & 255) == 255) before: movzbl %al, %eax cmpl $255, %eax after: cmpb $-1, %al git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182038 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix indentation.Akira Hatanaka2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182036 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Delete unused enum value.Akira Hatanaka2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182035 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TargetRegisterInfo::getCoveringLanes().Jakob Stoklund Olesen2013-05-16
| | | | | | | | This lane mask provides information about which register lanes completely cover super-registers. See the block comment before getCoveringLanes(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182034 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Use true offset value in "memrix" machine operandsUlrich Weigand2013-05-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the second part of the change to always return "true" offset values from getPreIndexedAddressParts, tackling the case of "memrix" type operands. This is about instructions like LD/STD that only have a 14-bit field to encode immediate offsets, which are implicitly extended by two zero bits by the machine, so that in effect we can access 16-bit offsets as long as they are a multiple of 4. The PowerPC back end currently handles such instructions by carrying the 14-bit value (as it will get encoded into the actual machine instructions) in the machine operand fields for such instructions. This means that those values are in fact not the true offset, but rather the offset divided by 4 (and then truncated to an unsigned 14-bit value). Like in the case fixed in r182012, this makes common code operations on such offset values not work as expected. Furthermore, there doesn't really appear to be any strong reason why we should encode machine operands this way. This patch therefore changes the encoding of "memrix" type machine operands to simply contain the "true" offset value as a signed immediate value, while enforcing the rules that it must fit in a 16-bit signed value and must also be a multiple of 4. This change must be made simultaneously in all places that access machine operands of this type. However, just about all those changes make the code simpler; in many cases we can now just share the same code for memri and memrix operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182032 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC32 cannot form counter loops around i64 FP conversionsHal Finkel2013-05-16
| | | | | | | On PPC32, i64 FP conversions are implemented using runtime calls (which clobber the counter register). These must be excluded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182023 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a triple to the test to try to fix the windows bots.Rafael Espindola2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182022 91177308-0d34-0410-b5e6-96231b3b80d8
* More addFrameMove test coverage.Rafael Espindola2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182021 91177308-0d34-0410-b5e6-96231b3b80d8
* Use new CHECK-DAG support to stabilize CodeGen/PowerPC/recipest.llBill Schmidt2013-05-16
| | | | | | | | | | While testing some experimental code to add vector-scalar registers to PowerPC, I noticed that a couple of independent instructions were flipped by the scheduler. The new CHECK-DAG support is perfect for avoiding this problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182020 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more addFrameMove test coverage.Rafael Espindola2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182019 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixing a 64-bit conversion warning in MSVC.Aaron Ballman2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182018 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more test coverage for addFrameMove.Rafael Espindola2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182017 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead calls to addFrameMove.Rafael Espindola2013-05-16
| | | | | | Without a PROLOG_LABEL present, the cfi instructions are never printed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182016 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Report true displacement value from getPreIndexedAddressPartsUlrich Weigand2013-05-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DAGCombiner::CombineToPreIndexedLoadStore calls a target routine to decompose a memory address into a base/offset pair. It expects the offset (if constant) to be the true displacement value in order to perform optional additional optimizations; in particular, to convert other uses of the original pointer into uses of the new base pointer after pre-increment. The PowerPC implementation of getPreIndexedAddressParts, however, simply calls SelectAddressRegImm, which returns a TargetConstant. This value is appropriate for encoding into the instruction, but it is not always usable as true displacement value: - Its type is always MVT::i32, even on 64-bit, where addresses ought to be i64 ... this causes the optimization to simply always fail on 64-bit due to this line in DAGCombiner: // FIXME: In some cases, we can be smarter about this. if (Op1.getValueType() != Offset.getValueType()) { - Its value is truncated to an unsigned 16-bit value if negative. This causes the above opimization to generate wrong code. This patch fixes both problems by simply returning the true displacement value (in its original type). This doesn't affect any other user of the displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182012 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more addFrameMove test coverage.Rafael Espindola2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182011 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend test to check the .cfi instructions.Rafael Espindola2013-05-16
| | | | | | | I am about to refactor the calls to addFrameMove and some of the ppc ones were not being tested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182009 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Tweak register array commentRichard Sandiford2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182007 91177308-0d34-0410-b5e6-96231b3b80d8
* Relax CHECK-NEXTs a bit to cope with atom's return nop padding.Benjamin Kramer2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181999 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Switch TLS globals to initial-exec model.Evgeniy Stepanov2013-05-16
| | | | | | | They are always defined in the main executable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181994 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed unused variable, detected by gccPatrik Hagglund2013-05-16
| | | | | | -Wunused-but-set-variable. Leftover from r181979. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181993 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete dead code.Rafael Espindola2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181982 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't call addFrameMove on XCore.Rafael Espindola2013-05-16
| | | | | | | | getExceptionHandlingType is not ExceptionHandling::DwarfCFI on xcore, so etFrameInstructions is never called. There is no point creating cfi instructions if they are never used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181979 91177308-0d34-0410-b5e6-96231b3b80d8
* Respect the 'nobuiltin' attribute when determining if a call is to a memory ↵Richard Smith2013-05-16
| | | | | | builtin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181978 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend test for better coverage.Rafael Espindola2013-05-16
| | | | | | | | | | | | | | | | | Without this change nothing was covering this addFrameMove: // For 64-bit SVR4 when we have spilled CRs, the spill location // is SP+8, not a frame-relative slot. if (Subtarget.isSVR4ABI() && Subtarget.isPPC64() && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { MachineLocation CSDst(PPC::X1, 8); MachineLocation CSSrc(PPC::CR2); MMI.addFrameMove(Label, CSDst, CSSrc); continue; } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181976 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed dead code.Rafael Espindola2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181975 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PBQP graph iterator typedefs.Lang Hames2013-05-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181973 91177308-0d34-0410-b5e6-96231b3b80d8
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