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* Cut the gold plugin README down to sizeAlp Toker2013-12-02
| | | | | | | This file hasn't been updated in years. Remove old information and point to the current documentation at GoldPlugin.rst. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196100 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix dominator descendants for unreachable blocks.Diego Novillo2013-12-02
| | | | | | | | | | | | | When a block is unreachable, asking its dom tree descendants should return the empty set. However, the computation of the descendants was causing a segmentation fault because the dom tree node we get from the basic block is initially NULL. Fixed by adding a test for a valid dom tree node before we iterate. The patch also adds some unit tests to the existing dom tree tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196099 91177308-0d34-0410-b5e6-96231b3b80d8
* [PM] [cleanup] Rearrange the public and private sections of this classChandler Carruth2013-12-02
| | | | | | | | | | | | to be a bit more sensible. The public interface now is first followed by the implementation details. This also resolves a FIXME to make something private -- it was already possible as the one special caller was already a friend. No functionality changed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196095 91177308-0d34-0410-b5e6-96231b3b80d8
* XCoreFrameLowering.cpp: Use [in,out] instead of [in] [out]. [-Wdocumentation]NAKAMURA Takumi2013-12-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196094 91177308-0d34-0410-b5e6-96231b3b80d8
* [CMake] add_lit_target: Tests should be excluded from "Build Solution".NAKAMURA Takumi2013-12-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196093 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Make handling of large frames not dependent upon an FP.Robert Lytton2013-12-02
| | | | | | | | | | | | eliminateFrameIndex() has been reworked to handle both small & large frames with either a FP or SP. An additional Slot is required for Scavenging spills when not using FP for large frames. Reworked the handling of Register Scavenging. Whether we are using an FP or not, whether it is a large frame or not, and whether we are using a large code model or not are now independent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196091 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: add pseudo-instructions for lit-pool global materialisationTim Northover2013-12-02
| | | | | | | | | | | | These are used by MachO only at the moment, and (much like the existing MOVW/MOVT set) work around the fact that the labels used in the actual instructions often contain PC-dependent components, which means that repeatedly materialising the same global can't be CSEed. With small modifications, it could be adapted to how ELF finds the address of _GLOBAL_OFFSET_TABLE_, which would give similar benefits in PIC mode there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196090 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore: Unbreak C++11 build.Benjamin Kramer2013-12-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196089 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: fix large code model 'select' indirect address handling.Robert Lytton2013-12-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196088 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Add large code modelRobert Lytton2013-12-02
| | | | | | | | | | | | | | | | When using large code model: Global objects larger than 'CodeModelLargeSize' bytes are placed in sections named with a trailing ".large" The folded global address of such objects are lowered into the const pool. During inspection it was noted that LowerConstantPool() was using a default offset of zero. A fix was made, but due to only offsets of zero being generated, testing only verifies the change is not detrimental. Correct the flags emitted for explicitly specified sections. We assume the size of the object queried by getSectionForConstant() is never greater than CodeModelLargeSize. To handle greater than CodeModelLargeSize, changes to AsmPrinter would be required. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196087 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: extend tests in preparationRobert Lytton2013-12-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196086 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Fix eliminateFrameIndex() to handle large framesRobert Lytton2013-12-02
| | | | | | | | Large frame offsets are loaded from the ConstantPool. Where possible, offsets are encoded using the smaller MKMSK instruction. Large frame offsets can only be used when there is a frame-pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196085 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Enable frames larger than 65535 to be loweredRobert Lytton2013-12-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196084 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an empty directory left after r194304, which incompletely reverted ↵Alexander Kornienko2013-12-02
| | | | | | r194218 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196081 91177308-0d34-0410-b5e6-96231b3b80d8
* [tsan] fix instrumentation of vector vptr updates ↵Kostya Serebryany2013-12-02
| | | | | | (https://code.google.com/p/thread-sanitizer/issues/detail?id=43) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196079 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the LTO GoldPlugin documentationAlp Toker2013-12-02
| | | | | | | | | * Update build instructions to reflect the current source tree layout. * Don't inflict CVS on readers; there's a perfectly good git mirror. * configure with --disable-werror making it possible to build using clang. * ar and nm-new now support the -plugin option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196069 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove leftovers from a non-MC asm printer.Rafael Espindola2013-12-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196068 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove #if 0 declarations.Rafael Espindola2013-12-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196067 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code.Rafael Espindola2013-12-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196066 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the default of AsmWriterClassName and isMCAsmWriter.Rafael Espindola2013-12-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196065 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename test with misspelt filenameAlp Toker2013-12-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196064 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead declarations.Rafael Espindola2013-12-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196063 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor for clarity and efficiency.Rafael Espindola2013-12-02
| | | | | | | The PPC GetSymbolFromOperand already prefixed stubs of MO_ExternalSymbol, so this should be a nop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196059 91177308-0d34-0410-b5e6-96231b3b80d8
* Also test the created stubs on 32 bits.Rafael Espindola2013-12-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196052 91177308-0d34-0410-b5e6-96231b3b80d8
* Add -mcpu to stackmap.llAndrew Trick2013-12-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196051 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix bug in -Oz stack adjustment foldingTim Northover2013-12-01
| | | | | | | | | | | Previously, we clobbered callee-saved registers when folding an "add sp, #N" into a "pop {rD, ...}" instruction. This change checks whether a register we're going to add to the "pop" could actually be live outside the function before doing so and should fix the issue. This should fix PR18081. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196046 91177308-0d34-0410-b5e6-96231b3b80d8
* Revamp error checking in the ms inline asm parser.Benjamin Kramer2013-12-01
| | | | | | | | | - Actually abort when an error occurred. - Check that the frontend lookup worked when parsing length/size/type operators. Tested by a clang test. PR18096. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196044 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure bitcode encoding of linkage types stays stable. Patch by Boaz OurielMichael Kuperstein2013-12-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196042 91177308-0d34-0410-b5e6-96231b3b80d8
* Use accessor methods instead.Bill Wendling2013-12-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196006 91177308-0d34-0410-b5e6-96231b3b80d8
* Use 'unsigned char' to get this past gcc error message:Bill Wendling2013-12-01
| | | | | | error: invalid conversion from 'unsigned char' to '{anonymous}::Sequence' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196004 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a scheduling model (with itinerary) for the PPC POWER7Hal Finkel2013-11-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a scheduling model for the POWER7 (P7) core, and enables the machine-instruction scheduler when targeting the P7. Scheduling for the P7, like earlier ooo PPC cores, requires considering both dispatch group hazards, and functional unit resources and latencies. These are both modeled in a combined itinerary. Dispatch group formation is still handled by the post-RA scheduler (which still needs to be updated for the P7, but nevertheless does a pretty good job). One interesting aspect of this change is that I've also enabled to use of AA duing CodeGen for the P7 (just as it is for the embedded cores). The benchmark results seem to support this decision (see below), and while this is normally useful for in-order cores, and not for ooo cores like the P7, I think that the dispatch slot hazards are enough like in-order resources to make the AA useful. Test suite significant performance differences (where negative is a speedup, and positive is a regression) vs. the current situation: MultiSource/Benchmarks/BitBench/drop3/drop3 with AA: N/A without AA: -28.7614% +/- 19.8356% (significantly against AA) MultiSource/Benchmarks/FreeBench/neural/neural with AA: -17.7406% +/- 11.2712% without AA: N/A (significantly in favor of AA) MultiSource/Benchmarks/SciMark2-C/scimark2 with AA: -11.2079% +/- 1.80543% without AA: -11.3263% +/- 2.79651% MultiSource/Benchmarks/TSVC/Symbolics-flt/Symbolics-flt with AA: -41.8649% +/- 17.0053% without AA: -34.5256% +/- 23.7072% MultiSource/Benchmarks/mafft/pairlocalalign with AA: 25.3016% +/- 17.8614% without AA: 38.6629% +/- 14.9391% (significantly in favor of AA) MultiSource/Benchmarks/sim/sim with AA: N/A without AA: 13.4844% +/- 7.18195% (significantly in favor of AA) SingleSource/Benchmarks/BenchmarkGame/Large/fasta with AA: 15.0664% +/- 6.70216% without AA: 12.7747% +/- 8.43043% SingleSource/Benchmarks/BenchmarkGame/puzzle with AA: 82.2713% +/- 26.3567% without AA: 75.7525% +/- 41.1842% SingleSource/Benchmarks/Misc/flops-2 with AA: -37.1621% +/- 20.7964% without AA: -35.2342% +/- 20.2999% (significantly in favor of AA) These are 99.5% confidence intervals from 5 runs per configuration. Regarding the choice to turn on AA during CodeGen, of these results, four seem significantly in favor of using AA, and one seems significantly against. I'm not making this decision based on these numbers alone, but these results seem consistent with results I have from other tests, and so I think that, on balance, using AA is a win. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195981 91177308-0d34-0410-b5e6-96231b3b80d8
* Split some PPC itinerary classesHal Finkel2013-11-30
| | | | | | | | | | | | | In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195980 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert a PPC test from grep to FileCheckHal Finkel2013-11-30
| | | | | | | | Convert this test to FileCheck, and improve it to check for the instructions it is trying to exclude instead of checking for register use (especially because grepping for r1 can be thrown off, for example, by a use of r12). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195979 91177308-0d34-0410-b5e6-96231b3b80d8
* Desensitize a couple of PPC regression testsHal Finkel2013-11-30
| | | | | | | Use CHECK-DAG to make these regression tests more resilient against changes in instruction scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195978 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the cpu specified on some PPC regression testsHal Finkel2013-11-30
| | | | | | | | | | | Some of these tests did not specify a cpu but were also sensitive to instruction scheduling and/or register assignment choices. A few others similarly-sensitive tests specified a cpu (often the POWER7), and while the P7 currently uses the default model for PPC64, this will soon change. For those tests which should not really be cpu-dependent anyway, the cpu is set to the generic 'ppc64'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195977 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for issue with microMIPS long branch.Zoran Jovanovic2013-11-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195976 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed issue with microMIPS long branch.Zoran Jovanovic2013-11-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195975 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] MSA loads and stores have a 10-bit offset. Account for this when ↵Daniel Sanders2013-11-30
| | | | | | | | | | lowering FrameIndex. This prevents the compiler from emitting invalid ld.[bhwd]'s and st.[bhwd]'s when the stack frame is between 512 and 32,768 bytes in size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195973 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] A small refactor to reduce patch noise in my next commitDaniel Sanders2013-11-30
| | | | | | | | No functional change. An if-statement has been split into two nested if-statements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195972 91177308-0d34-0410-b5e6-96231b3b80d8
* Force CPU type to unbreak unit tests on Haswell machines.Juergen Ributzka2013-11-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195971 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverse the order of eviction checks for possible compile time savings. No ↵Andrew Trick2013-11-29
| | | | | | functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195969 91177308-0d34-0410-b5e6-96231b3b80d8
* Part 1 of 3 patches that completes very long conditional branchesReed Kotler2013-11-29
| | | | | | | | | | | | | | in constant islands for Mips16. We introdcuce JalB16 as a synomnym for Jal16. It makes it easier to read and is also necessary because Jal16 is a call instruction but JalB16 is being used as a branch. Various parts of LLVM will not work properly even in this late stage of the backend if we use what was declared as a call instruction to function as a branch. For one, basic block labels may not get emitted in some situations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195968 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert revision 195965.Zoran Jovanovic2013-11-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195967 91177308-0d34-0410-b5e6-96231b3b80d8
* mips: XFAIL llvm-cov testPetar Jovanovic2013-11-29
| | | | | | | | XFAIL llvm-cov.test for MIPS until big-endian issues are fixed for llvm-cov. The test does pass on MIPS little-endian. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195966 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed issue with microMIPS long branch.Zoran Jovanovic2013-11-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195965 91177308-0d34-0410-b5e6-96231b3b80d8
* Adjust PPC A2 input operand latenciesHal Finkel2013-11-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the PPC A2, instructions are only issued after their input operands are ready. Model this by specifying that input operands are read at dispatch (0 cycles after issue). This changes all input operand latencies from 1 to 0. Significant test-suite performance changes (these are 99.5% confidence intervals on 6 runs for both before and after): speedups: MultiSource/Benchmarks/sim/sim -1.21915% +/- 0.175063% MultiSource/Benchmarks/TSVC/LinearDependence-flt/LinearDependence-flt -1.23946% +/- 1.05133% SingleSource/Benchmarks/Misc/flops-2 -1.24237% +/- 0.681362% MultiSource/Applications/JM/lencod/lencod -1.33992% +/- 0.757498% MultiSource/Benchmarks/TSVC/InductionVariable-flt/InductionVariable-flt -1.51802% +/- 1.21468% MultiSource/Benchmarks/TSVC/GlobalDataFlow-flt/GlobalDataFlow-flt -2.18818% +/- 1.28605% MultiSource/Benchmarks/TSVC/Packing-flt/Packing-flt -2.21977% +/- 1.19499% SingleSource/Benchmarks/BenchmarkGame/spectral-norm -2.29822% +/- 0.671871% MultiSource/Benchmarks/TSVC/Packing-dbl/Packing-dbl -2.40975% +/- 0.355931% SingleSource/Benchmarks/Misc/fp-convert -2.41899% +/- 1.04751% MultiSource/Benchmarks/TSVC/Searching-dbl/Searching-dbl -2.50349% +/- 0.126765% SingleSource/Benchmarks/Misc/flops-3 -3.00214% +/- 0.700795% MultiSource/Benchmarks/TSVC/LoopRestructuring-flt/LoopRestructuring-flt -3.56995% +/- 3.2929% MultiSource/Applications/sgefa/sgefa -4.24908% +/- 2.00413% MultiSource/Benchmarks/ASC_Sequoia/IRSmk/IRSmk -18.1294% +/- 3.96489% regressions: MultiSource/Benchmarks/TSVC/Reductions-dbl/Reductions-dbl 1.03249% +/- 0.178547% MultiSource/Applications/hexxagon/hexxagon 1.16597% +/- 0.285235% MultiSource/Benchmarks/TSVC/IndirectAddressing-flt/IndirectAddressing-flt 1.39576% +/- 1.07855% SingleSource/Benchmarks/Misc-C++/stepanov_v1p2 1.71539% +/- 0.173182% MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1 1.90013% +/- 0.866472% MultiSource/Benchmarks/TSVC/Recurrences-dbl/Recurrences-dbl 2.39854% +/- 1.05914% MultiSource/Benchmarks/TSVC/ControlFlow-dbl/ControlFlow-dbl 2.4402% +/- 0.817904% MultiSource/Benchmarks/TSVC/LoopRestructuring-dbl/LoopRestructuring-dbl 5.87997% +/- 3.3172% MultiSource/Benchmarks/Trimaran/netbench-crc/netbench-crc 9.02643% +/- 5.79591% MultiSource/Benchmarks/VersaBench/bmm/bmm 10.3517% +/- 1.227% Obviously, there are data points on both sides of this; but I think, overall, this supports making the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195951 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach LocalStackSlotAllocation that stackmaps/patchpoints don't have rangeLang Hames2013-11-29
| | | | | | | constraints on their frame offsets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195950 91177308-0d34-0410-b5e6-96231b3b80d8
* Create a PPC440 SchedMachineModelHal Finkel2013-11-29
| | | | | | | Some of the older PPC processor definitions don't have associated SchedMachineModels; correct this for the PPC440. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195949 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixup PPC440 load/store operand latenciesHal Finkel2013-11-29
| | | | | | | | The operand latencies for loads and stores in the PPC440 itinerary were wrong (the store operands are all inputs, and the "with update" (pre-increment) instructions need a latency for the additional output). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195948 91177308-0d34-0410-b5e6-96231b3b80d8
* Adjust PPC440 operand latenciesHal Finkel2013-11-29
| | | | | | | | | | | | The operand latencies for the PPC440 should be specified relative to dispatch, not relative to the initial fetch-and-decode stages. Because most instructions (ignoring bypass) wait in dispatch until their operands are ready, this is modeled as reading input operands "at dispatch" (0 cycles after issue), and so every input and output operand has 4 cycles subtracted from it. This could alter scheduling slightly, but I don't expect a large effect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195947 91177308-0d34-0410-b5e6-96231b3b80d8
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