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* Fix test so it doesn't try to write out temporary files into the test tree.David Blaikie2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211916 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid non-ascii character in the source code.Logan Chien2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211914 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Fix associative sections on COFFDavid Majnemer2014-06-27
| | | | | | | | | COFF sections in MC were represented by a tuple of section-name and COMDAT-name. This is not sufficient to represent a .text section associated with another .text section; we need a way to distinguish between the key section and the one marked associative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211913 91177308-0d34-0410-b5e6-96231b3b80d8
* [FastISel][X86] Fix typos.Juergen Ributzka2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211911 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Don't crash on unhandled instruction in promote allocaMatt Arsenault2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211906 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-objdump: don't assert if ELF file has no sectionsEd Maste2014-06-27
| | | | | | | | | | FreeBSD core files, for example, have no sections (only program headers). llvm.org/pr20139 Differential Revision: http://reviews.llvm.org/D4323 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211904 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up unused variable warning in release build.Alexander Kornienko2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211902 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply r211287: Remove support for LLVM runtime multi-threading.Chandler Carruth2014-06-27
| | | | | | | I'll fix the problems in libclang and other projects in ways that don't require <mutex> until we sort out the cygwin situation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211900 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Constrain base register in PPCRegisterInfo::resolveFrameIndexUlrich Weigand2014-06-27
| | | | | | | | | | | | | | | | | | | | | | | | I've run into a bug where current LLVM at -O0 (with fast-isel) generated invalid code like: ld 0, 20936(1) # 8-byte Folded Reload stw 12, 10348(0) stw 12, 10344(0) The underlying vreg had been introduced as base register by the Local Stack Slot Allocation pass. That register was constrained to G8RC by PPCRegisterInfo::materializeFrameBaseRegister to match the ADDI instruction used to set it, but it was *not* constrained to G8RC_NOX0 to fit the *use* of the register in an address. That should have happened in PPCRegisterInfo::resolveFrameIndex. This patch adds an appropriate constrainRegClass call. Reviewed by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211897 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Clean up some unused variables, especially in release builds.Chandler Carruth2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211894 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Teach the target combine step to aggressively fold pshufd insturcions.Chandler Carruth2014-06-27
| | | | | | | | | | | | | Summary: This allows it to fold pshufd instructions across intervening half-shuffles and other noise. This pattern actually shows up in the generic lowering tests, but I've also added direct tests using intrinsics to make sure that the specific desired functionality is working even if the lowering stuff changes in the future. Differential Revision: http://reviews.llvm.org/D4292 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211892 91177308-0d34-0410-b5e6-96231b3b80d8
* [ELF][Mips] Fix recognition of MIPS 64-bit arch in the ↵Simon Atanasyan2014-06-27
| | | | | | ELFObjectFile:getArch() method. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211891 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Teach the target-specific combining how to aggressively foldChandler Carruth2014-06-27
| | | | | | | | | | | | | | | | | | half-shuffles, even looking through intervening instructions in a chain. Summary: This doesn't happen to show up with any test cases I've found for the current shuffle lowering, but previous attempts would benefit from this and it seems generally useful. I've tested it directly using intrinsics, which also shows that it will work with hand vectorized code as well. Note that even though pshufd isn't directly used in these tests, it gets exercised because we combine some of the half shuffles into a pshufd first, and then merge them. Differential Revision: http://reviews.llvm.org/D4291 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211890 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Teach the X86 backend to DAG-combine SSE2 shuffles that areChandler Carruth2014-06-27
| | | | | | | | | | | | | | | | | trivially redundant. This fixes several cases in the new vector shuffle lowering algorithm which would generate redundant shuffle instructions for the sake of simplicity. I'm also deleting a testcase which was somewhat ridiculous. It was checking for a bug in 2007 about incorrectly transforming shuffles by looking for the string "-86" in the output of a pretty substantial function. This test case doesn't seem to have any value at this point. Differential Revision: http://reviews.llvm.org/D4240 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211889 91177308-0d34-0410-b5e6-96231b3b80d8
* [x86] Begin a significant overhaul of how vector lowering is done in theChandler Carruth2014-06-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | x86 backend. This sketches out a new code path for vector lowering, hidden behind an off-by-default flag while it is under development. The fundamental idea behind the new code path is to aggressively break down the problem space in ways that ease selecting the odd set of instructions available on x86, and carefully avoid scalarizing code even when forced to use older ISAs. Notably, this starts off restricting itself to SSE2 and implements the complete vector shuffle and blend space for 128-bit vectors in SSE2 without scalarizing. The plan is to layer on top of this ISA extensions where we can bail out of the complex SSE2 lowering and opt for a cheaper, specialized instruction (or set of instructions). It also needs to be generalized to AVX and AVX512 vector widths. Currently, this does a decent but not perfect job for SSE2. There are some specific shortcomings that I plan to address: - We need a peephole combine to fold together shuffles where possible. There are cases where a previous shuffle could be modified slightly to arrange for elements to be in the correct position and a later shuffle eliminated. Doing this eagerly added quite a bit of complexity, and so my plan is to combine away these redundancies afterward. - There are a lot more clever ways to use unpck and pack that need to be added. This is essential for real world shuffles as it turns out... Once SSE2 is polished a bit I should be able to get interesting numbers on performance improvements on benchmarks conducive to vectorization. All of this will be off by default until it is functionally equivalent of course. Differential Revision: http://reviews.llvm.org/D4225 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211888 91177308-0d34-0410-b5e6-96231b3b80d8
* [RuntimeDyld, PowerPC] Fix/improve handling of TOC relocationsUlrich Weigand2014-06-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current PPC64 RuntimeDyld code to handle TOC relocations has two problems: - With recent linkers, in addition to the relocations that implicitly refer to the TOC base (R_PPC64_TOC*), you can now also use the .TOC. magic symbol with any other relocation to refer to the TOC base explicitly. This isn't currently used much in ELFv1 code (although it could be), but it is essential in ELFv2 code. - In a complex JIT environment with multiple modules, each module may have its own .toc section, and TOC relocations in one module must refer to *its own* TOC section. The current findPPC64TOC implementation does not correctly implement this; in fact, it will always return the address of the first TOC section it finds anywhere. (Note that at the time findPPC64TOC is called, we don't even *know* which module the relocation originally resided in, so it is not even possible to fix this routine as-is.) This commit fixes both problems by handling TOC relocations earlier, in processRelocationRef. To do this, I've removed the findPPC64TOC routine and replaced it by a new routine findPPC64TOCSection, which works analogously to findOPDEntrySection in scanning the sections of the ObjImage provided by its caller, processRelocationRef. This solves the issue of finding the correct TOC section associated with the current module. This makes it straightforward to implement both R_PPC64_TOC relocations, and relocations explicitly refering to the .TOC. symbol, directly in processRelocationRef. There is now a new problem in implementing the R_PPC64_TOC16* relocations, because those can now in theory involve *three* different sections: the relocation may be applied in section A, refer explicitly to a symbol in section B, and refer implicitly to the TOC section C. The final processing of the relocation thus may only happen after all three of these sections have been assigned final addresses. There is currently no obvious means to implement this in its general form with the common-code RuntimeDyld infrastructure. Fortunately, ppc64 code usually makes no use of this most general form; in fact, TOC16 relocations are only ever generated by LLVM for symbols residing themselves in the TOC, which means "section B" == "section C" in the above terminology. This special case can easily be handled with the current infrastructure, and that is what this patch does. [ Unhandled cases result in an explicit error, unlike the current code which silently returns the wrong TOC base address ... ] This patch makes the JIT work on both BE and LE (ELFv2 requires additional patches, of course), and allowed me to successfully run complex JIT scenarios (via mesa/llvmpipe). Reviewed by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211885 91177308-0d34-0410-b5e6-96231b3b80d8
* IRReader: don't mark MemoryBuffers constAlp Toker2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211883 91177308-0d34-0410-b5e6-96231b3b80d8
* Added instruction combine to transform few more negative values addition to ↵Dinesh Dwivedi2014-06-27
| | | | | | | | | | | | | | subtraction (Part 3) This patch enables transforms for (x + (~(y | c) + 1) --> x - (y | c) if c is odd Differential Revision: http://reviews.llvm.org/D4210 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211881 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the caching of the target machine from SystemZTargetLowering.Eric Christopher2014-06-27
| | | | | | Update all callers and uses accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211880 91177308-0d34-0410-b5e6-96231b3b80d8
* GlobalOpt: Fix constantfold-initializers.ll testDavid Majnemer2014-06-27
| | | | | | | | | The test added in r211762 was sloppy, the correct initializer wasn't added to @llvm.global_ctors Spotted by Pasi Parviainen! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211879 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove target machine caching from SystemZInstrInfo andEric Christopher2014-06-27
| | | | | | | | SystemZRegisterInfo and replace it with the subtarget as that's all they needed in the first place. Update all uses and calls accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211877 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Revert "Revert "PR20038: DebugInfo: Inlined call sites where the ↵David Blaikie2014-06-27
| | | | | | | | | | | caller has debug info but the call itself has no debug location.""" Reverting this again, didn't mean to commit it - while r211872 fixes one of the issues here, there are still others to figure out and address. This reverts commit r211871. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211873 91177308-0d34-0410-b5e6-96231b3b80d8
* ArgumentPromotion: Propagate debug locations on calls for which arguments ↵David Blaikie2014-06-27
| | | | | | are promoted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211872 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Revert "PR20038: DebugInfo: Inlined call sites where the caller has ↵David Blaikie2014-06-27
| | | | | | | | debug info but the call itself has no debug location."" This reverts commit r211724. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211871 91177308-0d34-0410-b5e6-96231b3b80d8
* Have SystemZSelectionDAGInfo constructor take a DataLayout ratherEric Christopher2014-06-27
| | | | | | | than a target machine since it doesn't need anything past the DataLayout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211870 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename getX86ConditonCode -> getX86ConditionCodeCraig Topper2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211869 91177308-0d34-0410-b5e6-96231b3b80d8
* Left out the NDEBUG in the previous checkin.Andrew Trick2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211867 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineScheduler: add some book-keeping to fix an assert.Andrew Trick2014-06-27
| | | | | | | | Fixe for Bug 20057 - Assertion failied in llvm::SUnit* llvm::SchedBoundary::pickOnlyChoice(): Assertion `i <= (HazardRec->getMaxLookAhead() + MaxObservedStall) && "permanent hazard"' Thanks to Chad for the test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211865 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate const-correctness into parseBitcodeFile()Alp Toker2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211864 91177308-0d34-0410-b5e6-96231b3b80d8
* Have MipsSelectionDAGInfo constructor take a DataLayout ratherEric Christopher2014-06-27
| | | | | | | than a target machine since it doesn't need anything past the DataLayout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211863 91177308-0d34-0410-b5e6-96231b3b80d8
* ParseIR: don't take ownership of the MemoryBufferAlp Toker2014-06-27
| | | | | | | | | | clang was needlessly duplicating whole memory buffer contents in an attempt to satisfy unclear ownership semantics. Let's just hide internal LLVM quirks and present a simple non-owning interface. The public C API preserves previous behaviour for stability. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211861 91177308-0d34-0410-b5e6-96231b3b80d8
* Move NVPTX subtarget dependent variables from the target machineEric Christopher2014-06-27
| | | | | | to the subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211860 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add some testcases for promote alloca pass.Matt Arsenault2014-06-27
| | | | | | | More complicated GEPs are skipped. Add some tests to actually stress this skipping. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211859 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the target lowering we can get off of the DAG rather than offEric Christopher2014-06-27
| | | | | | of the cached target machine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211858 91177308-0d34-0410-b5e6-96231b3b80d8
* Support: update DLLCharacteristics enumerationSaleem Abdulrasool2014-06-27
| | | | | | | | Add the new AppContainer characteristic which is import for Windows Store (Metro) compatible applications. Add the new Control Flow Guard flag to bring the enumeration up to date with the current values as of Windows 8.1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211855 91177308-0d34-0410-b5e6-96231b3b80d8
* Support: tweak comment layoutSaleem Abdulrasool2014-06-27
| | | | | | Make the comment layout more uniform. NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211854 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't force the build of toos/lto as a static lib.Rafael Espindola2014-06-27
| | | | | | | | Any uses of tools/lto as a static lib should probably move to lib/LTO. This was also never implemented in the configure build, so this reduces the differences among the two. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211852 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix missing newline and simplify debug printing.Matt Arsenault2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211850 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Move load/store ReplaceNodeResults to common code.Matt Arsenault2014-06-27
| | | | | | Future patches will want to custom lower loads on SI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211848 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the constructor for NVPTXFrameLowering into the implementationEric Christopher2014-06-27
| | | | | | file in preparation for the subtarget move. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211847 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary caching of the TargetMachine on NVPTXFrameLowering.Eric Christopher2014-06-27
| | | | | | Adjust the constructor accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211846 91177308-0d34-0410-b5e6-96231b3b80d8
* Rework the logic for setting the TargetName. This appears toEric Christopher2014-06-27
| | | | | | be shorter and identical in goal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211845 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove caching of the target machine in NVPTXInstrInfo andEric Christopher2014-06-27
| | | | | | update constructor accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211840 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove comment that duplicated information in the constructorEric Christopher2014-06-27
| | | | | | that it's after. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211839 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove commented out code.Eric Christopher2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211838 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove extraneous parens and extraneous const cast (and fix theEric Christopher2014-06-27
| | | | | | prototype for the function to patch what we were returning). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211837 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the subtarget dependent features from the target machine toEric Christopher2014-06-27
| | | | | | the subtarget for the MSP430 target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211836 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove uses and caches of the target machine and subtarget fromEric Christopher2014-06-27
| | | | | | | | both MSP430InstrInfo and MSP430RegisterInfo. Remove unused member variable StackAlign from MSP430RegisterInfo. Update constructors accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211835 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove caching of an unused subtarget from MSP430FrameLowering.Eric Christopher2014-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211830 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] AVX512: Add vbroadcasti*Adam Nemet2014-06-27
| | | | | | | | | For now I used a separate template for these sub-vector/tuple broadcasts rather than sharing the mem variants with avx512_int_broadcast_rm. <rdar://problem/17402869> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211828 91177308-0d34-0410-b5e6-96231b3b80d8
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