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ScheduleDAG.h
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Author
Age
*
Explicitly request unsigned enum types when desired
Reid Kleckner
2013-10-08
*
Use SmallVectorImpl::iterator/const_iterator instead of SmallVector
Eric Christopher
2013-07-03
*
Machine Model: Add MicroOpBufferSize and resource BufferSize.
Andrew Trick
2013-06-15
*
MI Sched: eliminate local vreg copies.
Andrew Trick
2013-04-24
*
MI-Sched: schedule physreg copies.
Andrew Trick
2013-04-13
*
Fix incorrect ScheduleDAG comment and formalize Weak edges.
Andrew Trick
2013-03-01
*
Fix #includes, so we include only what we really need.
Jakub Staszak
2013-02-20
*
MachineScheduler support for viewGraph.
Andrew Trick
2013-01-25
*
ScheduleDAG: Added isBoundaryNode to conveniently detect a common corner case.
Andrew Trick
2013-01-25
*
MIsched: Added biasCriticalPath.
Andrew Trick
2013-01-24
*
Sort the #include lines for the include/... tree with the script.
Chandler Carruth
2012-12-03
*
misched: Don't consider artificial edges weak edges.
Andrew Trick
2012-11-13
*
misched: Infrastructure for weak DAG edges.
Andrew Trick
2012-11-12
*
misched: TargetSchedule interface for machine resources.
Andrew Trick
2012-11-06
*
ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.
Andrew Trick
2012-11-06
*
misched: Use the TargetSchedModel interface wherever possible.
Andrew Trick
2012-10-10
*
misched: remove forceUnitLatencies. Defaults are handled by the default Sched...
Andrew Trick
2012-10-08
*
Simplify the computeOperandLatency API.
Andrew Trick
2012-08-23
*
sched: Avoid trivially redundant DAG edges. Take the one with higher latency.
Andrew Trick
2012-06-13
*
misched: API for minimum vs. expected latency.
Andrew Trick
2012-06-05
*
misched: implemented a framework for top-down or bottom-up scheduling.
Andrew Trick
2012-03-14
*
misched preparation: rename core scheduler methods for consistency.
Andrew Trick
2012-03-07
*
misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.
Andrew Trick
2012-03-07
*
misched preparation: modularize schedule emission.
Andrew Trick
2012-03-07
*
misched preparation: modularize schedule printing.
Andrew Trick
2012-03-07
*
misched preparation: modularize schedule verification.
Andrew Trick
2012-03-07
*
Cleanup in preparation for misched: Move DAG visualization logic.
Andrew Trick
2012-03-07
*
Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ...
Andrew Trick
2012-03-07
*
misched comments
Andrew Trick
2012-03-07
*
Initialize SUnits before DAG building.
Andrew Trick
2012-02-22
*
Move some llvm_unreachable's from r149849 out of switch statements to satisfy...
Craig Topper
2012-02-06
*
Convert assert(0) to llvm_unreachable
Craig Topper
2012-02-05
*
Move Sched::Preference out of TargetMachine.h where it is not referenced.
Evan Cheng
2012-01-12
*
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_...
David Blaikie
2011-12-20
*
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
Evan Cheng
2011-06-28
*
Added -stress-sched flag in the Asserts build.
Andrew Trick
2011-06-15
*
Remove dead code.
Devang Patel
2011-06-02
*
Be careful about scheduling nodes above previous calls. It increase usages of
Evan Cheng
2011-04-26
*
Fix a ton of comment typos found by codespell. Patch by
Chris Lattner
2011-04-15
*
In the pre-RA scheduler, maintain cmp+br proximity.
Andrew Trick
2011-04-14
*
Added a check in the preRA scheduler for potential interference on a
Andrew Trick
2011-04-07
*
Typos.
Eric Christopher
2011-03-07
*
Introducing a new method of tracking register pressure. We can't
Andrew Trick
2011-02-04
*
Header warning patrol.
Eric Christopher
2010-12-25
*
Minor cleanup related to my latest scheduler changes.
Andrew Trick
2010-12-24
*
Various bits of framework needed for precise machine-level selection
Andrew Trick
2010-12-24
*
whitespace
Andrew Trick
2010-12-24
*
update comment.
Chris Lattner
2010-12-20
*
SDep is POD-like. Shave off a few bytes from SUnit by moving a member around.
Benjamin Kramer
2010-11-25
*
Two sets of changes. Sorry they are intermingled.
Evan Cheng
2010-11-03
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