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* misched: Heuristics based on the machine model.Andrew Trick2012-11-07
* misched: handle on-the-fly regpressure queries better for 2-addrAndrew Trick2012-11-07
* misched: TargetSchedule interface for machine resources.Andrew Trick2012-11-06
* ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.Andrew Trick2012-11-06
* Add extra declarations of hash_value needed to build llvm with xlc 12.1.Rafael Espindola2012-10-31
* [inline asm] Get the mayLoad/mayStore directly from the MIOp_ExtraInfo operand.Chad Rosier2012-10-30
* [inline asm] Implement mayLoad and mayStore for inline assembly. In general,Chad Rosier2012-10-30
* In various places throughout the code generator, there were specialUlrich Weigand2012-10-29
* Remove GC roots that reference dead objects.Nicolas Geoffray2012-10-26
* Use ilist rather than std::list for Node and Edge lists in the PBQP graph. ThisLang Hames2012-10-23
* Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerin...Nadav Rotem2012-10-18
* Change MachineFrameInfo::StackObject::Alloca from Value* to AllocaInst*Sebastian Pop2012-10-18
* Temporarily revert the TargetTransform changes.Bob Wilson2012-10-18
* Switch MRI::UsedPhysRegs to a register unit bit vector.Jakob Stoklund Olesen2012-10-17
* Add a really faster pre-RA scheduler (-pre-RA-sched=linearize). It doesn't useEvan Cheng2012-10-17
* Merge MRI::isPhysRegOrOverlapUsed() into isPhysRegUsed().Jakob Stoklund Olesen2012-10-17
* Use a SparseSet instead of a BitVector for UsedInInstr in RAFast.Jakob Stoklund Olesen2012-10-17
* Fix function parameter spelling in comments. Caught by -Wdocumentation.Dmitri Gribenko2012-10-16
* misched: Added handleMove support for updating all kill flags, not just for a...Andrew Trick2012-10-16
* Remove RegisterClassInfo::isReserved() and isAllocatable().Jakob Stoklund Olesen2012-10-15
* Remove LIS::isAllocatable() and isReserved() helpers.Jakob Stoklund Olesen2012-10-15
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-15
* Freeze the reserved registers as soon as isel is complete.Jakob Stoklund Olesen2012-10-15
* misched: ILP scheduler for experimental heuristics.Andrew Trick2012-10-15
* Remove unnecessary classof()'sSean Silva2012-10-11
* Change MachineInstrBuilder::addDisp to copy over target flags by default.Evan Cheng2012-10-11
* Add a new interface to allow IR-level passes to access codegen-specific infor...Nadav Rotem2012-10-10
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-10
* misched: Add computeInstrLatency to TargetSchedModel.Andrew Trick2012-10-09
* misched: Doxument the TargetSchedule API.Andrew Trick2012-10-09
* misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for ex...Andrew Trick2012-10-09
* misched: Remove LoopDependencies heuristic.Andrew Trick2012-10-09
* Add in some interfaces that will allow easier access to the pointer address s...Micah Villmow2012-10-09
* misched: remove forceUnitLatencies. Defaults are handled by the default Sched...Andrew Trick2012-10-08
* Move TargetData to DataLayout.Micah Villmow2012-10-08
* Remove unused MachineInstr constructors that don't take a DebugLoc argument.Craig Topper2012-10-07
* Switch MachineTraceMetrics to the new TargetSchedModel interface.Jakob Stoklund Olesen2012-10-04
* Revert 165051-165049 while looking into the foreach.m failure inEric Christopher2012-10-03
* Remove the SavePoint infrastructure from fast isel, replaceEric Christopher2012-10-02
* Fix PR13899Michael Liao2012-10-01
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. S...Sylvestre Ledru2012-09-27
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-27
* Revert r164663 due to buildbot failure.Craig Topper2012-09-26
* Add is16BitVector and is32BitVector to MVT and call them from EVT. Matches ot...Craig Topper2012-09-26
* Rename virtual table anchors from Anchor() to anchor() for consistency with t...Craig Topper2012-09-26
* Mark extended type querying methods as 'readonly' to reduce compile size.Craig Topper2012-09-26
* Add in new data types that are used by AMDIL/ANL among others.Micah Villmow2012-09-19
* Make MachinePostDominatorTree::DT privateTom Stellard2012-09-18
* TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick2012-09-18
* Merge into undefined lanes under -new-coalescer.Jakob Stoklund Olesen2012-09-17