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* Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.Jiangning Liu2013-11-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194085 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for AVX512 masked vector blend intrinsics.Cameron McInally2013-11-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194006 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: fixed a typo in builtin nameElena Demikhovsky2013-11-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193988 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added VPCONFLICT instruction and intrinsics,Elena Demikhovsky2013-11-03
| | | | | | | added EVEX_KZ to tablegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193959 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove linkonce_odr_auto_hide.Rafael Espindola2013-11-01
| | | | | | | | | | | | | | | linkonce_odr_auto_hide was in incomplete attempt to implement a way for the linker to hide symbols that are known to be available in every TU and whose addresses are not relevant for a particular DSO. It was redundant in that it all its uses are equivalent to linkonce_odr+unnamed_addr. Unlike those, it has never been connected to clang or llvm's optimizers, so it was effectively dead. Given that nothing produces it, this patch just nukes it (other than the llvm-c enum value). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193865 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar fixed-point convert to floating-point ↵Chad Rosier2013-10-31
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193816 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new calling convention for WebKit Java Script.Andrew Trick2013-10-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193812 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar shift immediate instructions.Chad Rosier2013-10-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193790 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup: update comments.Manman Ren2013-10-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193773 91177308-0d34-0410-b5e6-96231b3b80d8
* Add experimental stackmap intrinsics to definition file and documenation.Andrew Trick2013-10-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193767 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable variable arguments support for intrinsics.Andrew Trick2013-10-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193766 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX512 unmasked integer broadcast intrinsics and support.Cameron McInally2013-10-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193748 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related testsDaniel Sanders2013-10-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193695 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from ↵Daniel Sanders2013-10-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | normal IR (i.e. not intrinsics) Also corrected the definition of the intrinsics for these instructions (the result register is also the first operand), and added intrinsics for bsel and bseli to clang (they already existed in the backend). These four operations are mostly equivalent to bsel, and bseli (the difference is which operand is tied to the result). As a result some of the tests changed as described below. bitwise.ll: - bsel.v test adapted so that the mask is unknown at compile-time. This stops it emitting bmnzi.b instead of the intended bsel.v. - The bseli.b test now tests the right thing. Namely the case when one of the values is an uimm8, rather than when the condition is a uimm8 (which is covered by bmnzi.b) compare.ll: - bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this is the same operation (see MSA.txt). i8.ll - CHECK-DAG-ized test. - bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands because this is the same operation (see MSA.txt). - bseli.b still emits bseli.b though because the immediate makes it distinguishable from bmnzi.b. vec.ll: - CHECK-DAG-ized test. - bmz.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). - bsel.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193693 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar floating-point compare instructions.Chad Rosier2013-10-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193691 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor the AVX512 intrinsics. Cluster the intrinsics into the appropriate ↵Cameron McInally2013-10-30
| | | | | | vector extension class within the .td file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193690 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. ↵Daniel Sanders2013-10-30
| | | | | | | | | | | | | | | | | | | not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8
* Clarify that GlobalVariables definitions must have an initializer.Rafael Espindola2013-10-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193609 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: PMIN/PMAX intrinsics and patternsElena Demikhovsky2013-10-27
| | | | | | | Patch by Cameron McInally <cameron.mcinally@nyu.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193497 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r193251 : Use address-taken to disambiguate global variable and ↵Shuxin Yang2013-10-27
| | | | | | indirect memops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193489 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added VCVTPH2PS, VCVTPS2PH with intrinsicsElena Demikhovsky2013-10-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193312 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed doxygen comment to match Module.cppYuchen Wu2013-10-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193273 91177308-0d34-0410-b5e6-96231b3b80d8
* Use address-taken to disambiguate global variable and indirect memops.Shuxin Yang2013-10-23
| | | | | | | | | | | Major steps include: 1). introduces a not-addr-taken bit-field in GlobalVariable 2). GlobalOpt pass sets "not-address-taken" if it proves a global varirable dosen't have its address taken. 3). AA use this info for disambiguation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193251 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add the constraint to NEON scalar mla/mls instructions.Chad Rosier2013-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193117 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Fix definition of SLD instruction.Matheus Almeida2013-10-21
| | | | | | | | | The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193076 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar three register different instructionChad Rosier2013-10-17
| | | | | | | | class. The instruction class includes the signed saturating doubling multiply-add long, signed saturating doubling multiply-subtract long, and the signed saturating doubling multiply long instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192908 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added lsa instructionDaniel Sanders2013-10-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192895 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Removed ldx.[bhwd] and stx.[bhwd].Daniel Sanders2013-10-17
| | | | | | | | | | These were present in a previous version of the MSA spec but are not present in the published version. There is no hardware that uses these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192888 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar negate instruction.Chad Rosier2013-10-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192843 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar absolute value instruction.Chad Rosier2013-10-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192842 91177308-0d34-0410-b5e6-96231b3b80d8
* Update comment.Chad Rosier2013-10-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192806 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar signed saturating accumulated of unsignedChad Rosier2013-10-16
| | | | | | value and unsigned saturating accumulate of signed value instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192800 91177308-0d34-0410-b5e6-96231b3b80d8
* TypeFinder: prefer iterative algorithm to keep stack usage low.Will Dietz2013-10-16
| | | | | | | Introduce subtype_reverse_iterator to maintain the numbering assigned during the recursive type walk. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192770 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove x86_sse42_crc32_64_8 intrinsic. It has no functional difference from ↵Craig Topper2013-10-15
| | | | | | x86_sse42_crc32_32_8 and was not mapped to a clang builtin. I'm not even sure why this form of the instruction is even called out explicitly in the docs. Also add AutoUpgrade support to convert it into the other intrinsic with appropriate trunc and zext. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192672 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar integer compare instructions.Chad Rosier2013-10-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192596 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a GlobalAlias::isValidLinkage to reduce code duplication.Rafael Espindola2013-10-09
| | | | | | Thanks to Reid Kleckner for the suggestion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192298 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.Elena Demikhovsky2013-10-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192283 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar floating-point reciprocal estimate,Chad Rosier2013-10-08
| | | | | | reciprocal exponent, and reciprocal square root estimate instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192242 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix duplicated assertions.Matt Arsenault2013-10-08
| | | | | | Do what some other instructions do, and add an assert method. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192236 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar signed/unsigned integer to floating-pointChad Rosier2013-10-08
| | | | | | convert instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192231 91177308-0d34-0410-b5e6-96231b3b80d8
* IRBuilder: Downgrade InsertPointGuard's instruction pointer to a raw pointer.Benjamin Kramer2013-10-08
| | | | | | | | Sadly this loses the checking from AssertingVH, but apparently storing the end() of a BasicBlock into an AssertingVH has bad consequences as it's not really an instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192209 91177308-0d34-0410-b5e6-96231b3b80d8
* Change objectsize intrinsic to accept different address spaces.Matt Arsenault2013-10-07
| | | | | | | Bitcasting everything to i8* won't work. Autoupgrade the old intrinsic declarations to use the new mangling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192117 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added scalar convert instructions and intrinsics.Elena Demikhovsky2013-10-06
| | | | | | | Fixed load folding in VPERM2I instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192063 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns ↵Craig Topper2013-10-05
| | | | | | are sufficient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192039 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement aarch64 neon instruction set AdvSIMD (Across).Jiangning Liu2013-10-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192028 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns for selecting TBM instructions from logical operations. Patch ↵Craig Topper2013-10-03
| | | | | | from Yunzhong Gao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191871 91177308-0d34-0410-b5e6-96231b3b80d8
* Add v4f16 to supported value types.Pete Cooper2013-10-03
| | | | | | | This is useful for some ARM intrinsics such as VCVTN which does a <4 x float> <-> <4 x half> conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191870 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Introduce the 'sevl' instruction in ARMv8.Joey Gouly2013-10-01
| | | | | | | | This also removes the restriction on the immediate field of the 'hint' instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8
* IRBuilder: Add RAII objects to reset insertion points or fast math flags.Benjamin Kramer2013-09-30
| | | | | | | | Inspired by the object from the SLPVectorizer. This found a minor bug in the debug loc restoration in the vectorizer where the location of a following instruction was attached instead of the location from the original instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191673 91177308-0d34-0410-b5e6-96231b3b80d8
* IRBuilder: Move fast math flags to IRBuilderBase.Benjamin Kramer2013-09-30
| | | | | | They don't depend on the templated stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191672 91177308-0d34-0410-b5e6-96231b3b80d8
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