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path: root/include/llvm/IntrinsicsARM.td
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* Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairsBruno Cardoso Lopes2011-05-28
| | | | | | | | to load/store i64 values. Since there's no current support to explicitly declare such restrictions, implement it by using specific hardcoded register pairs during isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a few ARM coprocessor intrinsics. Testcases includedBruno Cardoso Lopes2011-05-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130763 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert a minor comment change inadvertently included with r128502.Bob Wilson2011-03-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128526 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. FrontendsEvan Cheng2011-03-29
| | | | | | | | | | | | | | | | was lowering them to sext / uxt + mul instructions. Unfortunately the optimization passes may hoist the extensions out of the loop and separate them. When that happens, the long multiplication instructions can be broken into several scalar instructions, causing significant performance issue. Note the vmla and vmls intrinsics are not added back. Frontend will codegen them as intrinsics vmull* + add / sub. Also note the isel optimizations for catching mul + sext / zext are not changed either. First part of rdar://8832507, rdar://9203134 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128502 91177308-0d34-0410-b5e6-96231b3b80d8
* ptx: add basic intrinsic supportChe-Liang Chiou2011-03-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127084 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Neon VCVT instructions for f32 <-> f16 conversions.Bob Wilson2010-12-15
| | | | | | | Clang is now providing intrinsics for these and so we need to support them in the backend. Radar 8068427. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121902 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace NEON vabdl, vaba, and vabal intrinsics with combinations of theBob Wilson2010-09-03
| | | | | | | | | vabd intrinsic and add and/or zext operations. In the case of vaba, this also avoids the need for a DAG combine pattern to combine vabd with add. Update tests. Auto-upgrade the old intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112941 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,Bob Wilson2010-09-01
| | | | | | | | add, and subtract operations with zero-extended or sign-extended vectors. Update tests. Add auto-upgrade support for the old intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112773 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NEON vmovn intrinsic, replacing it with vector truncate operations.Bob Wilson2010-08-30
| | | | | | | Auto-upgrade the old intrinsic and update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112507 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvmBob Wilson2010-08-29
| | | | | | | | IR add/sub operations with one or both operands sign- or zero-extended. Auto-upgrade the old intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112416 91177308-0d34-0410-b5e6-96231b3b80d8
* Add alignment arguments to all the NEON load/store intrinsics.Bob Wilson2010-08-27
| | | | | | | | Update all the tests using those intrinsics and add support for auto-upgrading bitcode files with the old versions of the intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112271 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend andBob Wilson2010-08-20
| | | | | | | zero-extend operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111614 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMemDan Gohman2010-08-05
| | | | | | | to IntrReadWriteArgMem, as it's for reading as well as writing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for getting & setting the FPSCR application register on ARM when ↵Nate Begeman2010-08-03
| | | | | | | | | | VFP is enabled. Add support for using the FPSCR in conjunction with the vcvtr instruction, for controlling fp to int rounding. Add support for the FLT_ROUNDS_ node now that the FPSCR is exposed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110152 91177308-0d34-0410-b5e6-96231b3b80d8
* Add builtins for ssat/usat, similar to RealView's __ssat and __usat intrinsics.Nate Begeman2010-07-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109813 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to ↵Nate Begeman2010-07-29
| | | | | | | | | the QADD & QSUB instructions. Behave identically to __qadd & __qsub RealView instruction intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109770 91177308-0d34-0410-b5e6-96231b3b80d8
* [llvm_void_ty] is no longer needed for result types, Chris Lattner2010-03-23
| | | | | | | just use an empty result list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99346 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new intrinsics for Neon vldN_lane and vstN_lane operations.Bob Wilson2009-08-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79716 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these asBob Wilson2009-08-21
| | | | | | | | vector shuffles. Temporarily remove the tests for these operations until the new implementation is working. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79579 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some comments to clarify the arguments to the vtbl and vtbx intrinsics.Bob Wilson2009-08-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78775 91177308-0d34-0410-b5e6-96231b3b80d8
* Use vAny type to get rid of Neon intrinsics that differed only in whetherBob Wilson2009-08-11
| | | | | | | | | | | | the overloaded vector types allowed floating-point or integer vector elements. Most of these operations actually depend on the element type, so bitcasting was not an option. If you include the vpadd intrinsics that I updated earlier, this gets rid of 20 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78646 91177308-0d34-0410-b5e6-96231b3b80d8
* Use new EVT::vAny type to combine Neon intrinsics for VPADD.Bob Wilson2009-08-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78632 91177308-0d34-0410-b5e6-96231b3b80d8
* Change Neon table lookup (VTBL) and table extension (VTBX) intrinsics toBob Wilson2009-08-09
| | | | | | | | take the table vectors as separate arguments, instead of the previous approach where they were combined into one big vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78525 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new intrinsics for Neon VTRN, VZIP and VUZP operations. Modeling theseBob Wilson2009-08-07
| | | | | | | | | | | as vector shuffles did not work out well. Shuffles that produce double-wide vectors accurately represent the operation but make it hard to do anything with the results. I considered splitting them up into 2 shuffles, one to write each register separately, but there doesn't seem to be a good way to reunite them for codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78437 91177308-0d34-0410-b5e6-96231b3b80d8
* Change Neon VLDn intrinsics to return multiple values instead of reallyBob Wilson2009-07-29
| | | | | | | | wide vectors. Likewise, change VSTn intrinsics to take separate arguments for each vector in a multi-vector struct. Adjust tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77468 91177308-0d34-0410-b5e6-96231b3b80d8
* Change NEON vldN/vstN intrinsics to specify "N" as an immediate operandBob Wilson2009-07-07
| | | | | | | instead of having a separate intrinsic for each value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74958 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing argument for vtbx intrinsic.Bob Wilson2009-06-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74340 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics for ARM NEON vtbl and vtbx operations.Bob Wilson2009-06-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74333 91177308-0d34-0410-b5e6-96231b3b80d8
* Swap order of arguments to vst[34]* intrinsics. This matches the orderBob Wilson2009-06-26
| | | | | | | | used by both the user-visible intrinsics defined by ARM and the corresponding GCC builtins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74300 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for ARM's Advanced SIMD (NEON) instruction set.Bob Wilson2009-06-22
| | | | | | | | This is still a work in progress but most of the NEON instruction set is supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify the intrinsics pattern to separate out the "return" types from theBill Wendling2008-11-13
| | | | | | | | | | | | "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
* remove attribution from a variety of miscellaneous files.Chris Lattner2007-12-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45425 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Implement __builtin_thread_pointer.Lauro Ramos Venancio2007-11-08
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43892 91177308-0d34-0410-b5e6-96231b3b80d8
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