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* [DAGCombiner] Reapply load slicing (192471) with a test that explicitly set ↵Quentin Colombet2013-10-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sse4.2 support. This should fix the buildbots. Original commit message: [DAGCombiner] Slice a big load in two loads when the element are next to each other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192476 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Revert load slicing (r192471), until I figure out why it fails ↵Quentin Colombet2013-10-11
| | | | | | on ubuntu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192474 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Slice a big load in two loads when the element are next to eachQuentin Colombet2013-10-11
| | | | | | | | | | | | | | | | | | | | | | | | | other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192471 91177308-0d34-0410-b5e6-96231b3b80d8
* Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom ↵Justin Holewinski2013-10-11
| | | | | | | | | | | | | comments for implicit defs For NVPTX, this fixes a crash where the emitImplicitDef implementation was expecting physical registers, while NVPTX uses virtual registers (with a couple of exceptions). Now, the implicit def comment will be emitted as a true PTX register name. Other targets can use this to customize the output of implicit def comments. Fixes PR17519 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192444 91177308-0d34-0410-b5e6-96231b3b80d8
* Print register in LiveInterval::print()Matthias Braun2013-10-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192398 91177308-0d34-0410-b5e6-96231b3b80d8
* Represent RegUnit liveness with LiveRange instanceMatthias Braun2013-10-10
| | | | | | | Previously LiveInterval has been used, but having a spill weight and register number is unnecessary for a register unit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192397 91177308-0d34-0410-b5e6-96231b3b80d8
* Work on LiveRange instead of LiveInterval where possibleMatthias Braun2013-10-10
| | | | | | | Also change some pointer arguments to references at some places where 0-pointers are not allowed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192396 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass LiveQueryResult by valueMatthias Braun2013-10-10
| | | | | | | This makes the API a bit more natural to use and makes it easier to make LiveRanges implementation details private. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192394 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor LiveInterval: introduce new LiveRange classMatthias Braun2013-10-10
| | | | | | | | | | LiveRange just manages a list of segments and a list of value numbers now as LiveInterval did previously, but without having details like spill weight or a fixed register number. LiveInterval is now a subclass of LiveRange and simply adds the spill weight and the register number. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192393 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename LiveRange to LiveInterval::SegmentMatthias Braun2013-10-10
| | | | | | | | The Segment struct contains a single interval; multiple instances of this struct are used to construct a live range, but the struct is not a live range by itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192392 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename parameter: defined regs are not incoming.Matthias Braun2013-10-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192391 91177308-0d34-0410-b5e6-96231b3b80d8
* test commitSriram Murali2013-10-10
| | | | | | | | - fix comments on vector type legalization git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192389 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix grammar / missing wordsMatt Arsenault2013-10-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192380 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: In DIBuilder, the context field of subprogram is updated to useManman Ren2013-10-10
| | | | | | | | | DIScopeRef. A paired commit at clang is required due to changes to DIBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192378 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-10
| | | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Implement AArch64 vector load/store multiple N-element structure ↵Rafael Espindola2013-10-10
| | | | | | | | class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." This reverts commit r192352. It broke the build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-10
| | | | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: In DIBuilder, the context and type fields of template_type andManman Ren2013-10-09
| | | | | | | | | template_value are updated to use DIRef. A paired commit at clang is required due to changes to DIBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192320 91177308-0d34-0410-b5e6-96231b3b80d8
* Flip the ownership of MCStreamer and MCTargetStreamer.Benjamin Kramer2013-10-09
| | | | | | | MCStreamer now owns the target streamer. This prevents leaking the target streamer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192303 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a GlobalAlias::isValidLinkage to reduce code duplication.Rafael Espindola2013-10-09
| | | | | | Thanks to Reid Kleckner for the suggestion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192298 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.Elena Demikhovsky2013-10-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192283 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar floating-point reciprocal estimate,Chad Rosier2013-10-08
| | | | | | reciprocal exponent, and reciprocal square root estimate instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192242 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix duplicated assertions.Matt Arsenault2013-10-08
| | | | | | Do what some other instructions do, and add an assert method. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192236 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar signed/unsigned integer to floating-pointChad Rosier2013-10-08
| | | | | | convert instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192231 91177308-0d34-0410-b5e6-96231b3b80d8
* Explicitly request unsigned enum types when desiredReid Kleckner2013-10-08
| | | | | | | This fixes repeated -Wmicrosoft warnings when self-hosting clang on Windows, and gets us real unsigned enum types with MSVC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192227 91177308-0d34-0410-b5e6-96231b3b80d8
* Move DIRef::getName out of line.Manman Ren2013-10-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192214 91177308-0d34-0410-b5e6-96231b3b80d8
* IRBuilder: Downgrade InsertPointGuard's instruction pointer to a raw pointer.Benjamin Kramer2013-10-08
| | | | | | | | Sadly this loses the checking from AssertingVH, but apparently storing the end() of a BasicBlock into an AssertingVH has bad consequences as it's not really an instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192209 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a MCTargetStreamer interface.Rafael Espindola2013-10-08
| | | | | | | | | | | | | This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
* update mach-o EXPORT_SYMBOL_* namesNick Kledzik2013-10-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192151 91177308-0d34-0410-b5e6-96231b3b80d8
* Formally added an explicit enum for DWARF TLS support. No functionality change.Richard Mitton2013-10-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192118 91177308-0d34-0410-b5e6-96231b3b80d8
* Change objectsize intrinsic to accept different address spaces.Matt Arsenault2013-10-07
| | | | | | | Bitcasting everything to i8* won't work. Autoupgrade the old intrinsic declarations to use the new mangling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192117 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code.Rafael Espindola2013-10-07
| | | | | | | | | Support for exception handling in the legacy JIT was removed in r181354 and this code was dead since then. Thanks to Yaron Keren for noticing it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192101 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the documentation of getDefaultSubtargetFeatures.Rafael Espindola2013-10-07
| | | | | | Patch by David Nadlinger. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192098 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Revert "Windows: Add support for unicode command lines""David Majnemer2013-10-07
| | | | | | | | This reverts commit r192070 which reverted r192069, I forgot to regenerate the configure scripts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192079 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Windows: Add support for unicode command lines"David Majnemer2013-10-06
| | | | | | | | This is causing MinGW bots to fail. This reverts commit r192069. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192070 91177308-0d34-0410-b5e6-96231b3b80d8
* Windows: Add support for unicode command linesDavid Majnemer2013-10-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The MSVCRT deliberately sends main() code-page specific characters. This isn't too useful to LLVM as we end up converting the arguments to UTF-16 and subsequently attempt to use the result as, for example, a file name. Instead, we need to have the ability to access the Unicode command line and transform it to UTF-8. This has the distinct advantage over using the MSVC-specific wmain() function as our entry point because: - It doesn't work on cygwin. - It only work on MinGW with caveats and only then on certain versions. - We get to keep our entry point as main(). :) N.B. This patch includes fixes to other parts of lib/Support/Windows s.t. we would be able to take advantage of getting the Unicode paths. E.G. clang spawning clang -cc1 would want to give it Unicode arguments. Reviewers: aaron.ballman, Bigcheese, rnk, ruiu Reviewed By: rnk CC: llvm-commits, ygao Differential Revision: http://llvm-reviews.chandlerc.com/D1834 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192069 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added scalar convert instructions and intrinsics.Elena Demikhovsky2013-10-06
| | | | | | | Fixed load folding in VPERM2I instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192063 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips] Add MIPS program header types.Simon Atanasyan2013-10-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192059 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns ↵Craig Topper2013-10-05
| | | | | | are sufficient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192039 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some really nasty uses of hasRawTextSupport.Rafael Espindola2013-10-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When MC was first added, targets could use hasRawTextSupport to keep features working before they were added to the MC interface. The design goal of MC is to provide an uniform api for printing assembly and object files. Short of relaxations and other corner cases, a object file is just another representation of the assembly. It was never the intention that targets would keep doing things like if (hasRawTextSupport()) Set flags in one way. else Set flags in another way. When they do that they create two code paths and the object file is no longer just another representation of the assembly. This also then requires testing with llc -filetype=obj, which is extremelly brittle. This patch removes some of these hacks by replacing them with smaller ones. The ARM flag setting is trivial, so I just moved it to the constructor. For Mips, the patch adds two temporary hack directives that allow the assembly to represent the same things as the object file was already able to. The hope is that the mips developers will replace the hack directives with the same ones that gas uses and drop the -print-hack-directives flag. I will also try to implement a target streamer interface, so that we can move this out of the common code. In summary, for any new work, two rules of the thumb are * Don't use "llc -filetype=obj" in tests. * Don't add calls to hasRawTextSupport. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192035 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement aarch64 neon instruction set AdvSIMD (Across).Jiangning Liu2013-10-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192028 91177308-0d34-0410-b5e6-96231b3b80d8
* Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences ↵Craig Topper2013-10-05
| | | | | | of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192026 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: In DIBuilder, the derived-from field of a DW_TAG_pointer_typeManman Ren2013-10-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | is updated to use DITypeRef. Move isUnsignedDIType and getOriginalTypeSize from DebugInfo.h to be static helper functions in DwarfCompileUnit. We already have a static helper function "isTypeSigned" in DwarfCompileUnit, and a pointer to DwarfDebug is added to resolve the derived-from field. All three functions need to go across link for derived-from fields, so we need to get hold of a type identifier map. A pointer to DwarfDebug is also added to DbgVariable in order to resolve the derived-from field. Debug info verifier is updated to check a derived-from field is a TypeRef. Verifier will not go across link for derived-from fields, in debug info finder, we go across the link to add derived-from fields to types. Function getDICompositeType is only used by dragonegg and since dragonegg does not generate identifier for types, we use an empty map to resolve the derived-from field. When printing a derived-from field, we use DITypeRef::getName to either return the type identifier or getName of the DIType. A paired commit at clang is required due to changes to DIBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192018 91177308-0d34-0410-b5e6-96231b3b80d8
* Pull this out for a bit of readability.Eric Christopher2013-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191999 91177308-0d34-0410-b5e6-96231b3b80d8
* Reformat.Eric Christopher2013-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191997 91177308-0d34-0410-b5e6-96231b3b80d8
* Formatting.Eric Christopher2013-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191995 91177308-0d34-0410-b5e6-96231b3b80d8
* reverting per requestJack Carter2013-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191992 91177308-0d34-0410-b5e6-96231b3b80d8
* [MC][AsmParser] Hook for post assembly file processingJack Carter2013-10-04
| | | | | | | | | | | | | | | | | | | | | | This patch handles LLVM standalone assembler (llvm-mc) ELF flag setting based on input file directive processing. Mips assembly requires processing inline directives that directly and indirectly affect the output ELF header flags. This patch handles one ".abicalls". To process these directives we are following the model the code generator uses by storing state in a container as we go through processing and when we detect the end of input file processing, AsmParser is notified and we update the ELF header flags through a MipsELFStreamer method with a call from MCTargetAsmParser::emitEndOfAsmFile(MCStreamer &OutStreamer). This patch will allow other targets the same functionality. Jack git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191982 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert r191792 as it is causing some LTO debug failuresEric Christopher2013-10-04
| | | | | | | on platforms with relocations in debug info and also temporarily revert r191800 due to conflicts with the revert of r191792. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191967 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r191940 to see if it fixes the build bots.Craig Topper2013-10-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191941 91177308-0d34-0410-b5e6-96231b3b80d8
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