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path: root/lib/CodeGen/LLVMTargetMachine.cpp
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* Stop using the dom frontier in DwarfEHPrepare by not promoting alloca'sDuncan Sands2010-08-31
| | | | | | | | | any more. I plan to reimplement alloca promotion using SSAUpdater later. It looks like Bill's URoR logic really always needs domtree, so the pass now always asks for domtree info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112597 91177308-0d34-0410-b5e6-96231b3b80d8
* Move enabling the local stack allocation pass into the target where it belongs.Jim Grosbach2010-08-24
| | | | | | | For now it's still a command line option, but the interface to the generic code doesn't need to know that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111942 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a local stack object block allocation pass. This is still anJim Grosbach2010-08-14
| | | | | | | | | | | | | | | | | | | | experimental pass that allocates locals relative to one another before register allocation and then assigns them to actual stack slots as a block later in PEI. This will eventually allow targets with limited index offset range to allocate additional base registers (not just FP and SP) to more efficiently reference locals, as well as handle situations where locals cannot be referenced via SP or FP at all (dynamic stack realignment together with variable sized objects, for example). It's currently incomplete and almost certainly buggy. Work in progress. Disabled by default and gated via the -enable-local-stack-alloc command line option. rdar://8277890 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111059 91177308-0d34-0410-b5e6-96231b3b80d8
* tidy up whitespace a bitJim Grosbach2010-08-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111019 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge the OptimizeExts and OptimizeCmps passes into one PeepholeOptimizerBill Wendling2010-08-09
| | | | | | | | pass. This pass should expand with all of the small, fine-grained optimization passes to reduce compile time and increase happiment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110627 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the Optimize Compares pass (disabled by default).Bill Wendling2010-08-06
| | | | | | | | | | | | | | | | | This pass tries to remove comparison instructions when possible. For instance, if you have this code: sub r1, 1 cmp r1, 0 bz L1 and "sub" either sets the same flag as the "cmp" instruction or could be converted to set the same flag, then we can eliminate the "cmp" instruction all together. This is a important for ARM where the ALU instructions could set the CPSR flag, but need a special suffix ('s') to do so. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110423 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove double-def checking from MachineVerifier, so a register does not have toJakob Stoklund Olesen2010-08-05
| | | | | | | | | | be killed before being redefined. These checks are usually disabled, and usually fail when enabled. We de facto allow live registers to be redefined without a kill, the corresponding assertions in RegScavenger were removed long ago. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110362 91177308-0d34-0410-b5e6-96231b3b80d8
* The lower invoke pass needs to have unreachable code elimination run after itBill Wendling2010-08-04
| | | | | | | because it could create such things. This fixes a MingW buildbot test failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110279 91177308-0d34-0410-b5e6-96231b3b80d8
* The EH prepare passes really want to be the last passes run before code-gen.Bill Wendling2010-08-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110248 91177308-0d34-0410-b5e6-96231b3b80d8
* Plug the remaining MC leaks by giving MCObjectStreamer/MCAsmStreamer ↵Benjamin Kramer2010-07-29
| | | | | | ownership of the TargetAsmBackend and the MCCodeEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109767 91177308-0d34-0410-b5e6-96231b3b80d8
* Add hook to insert late LLVM=>LLVM passes just before iselAnton Korobeynikov2010-07-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109354 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial modifications to MCAssembler and TargetMachine for the MCJIT.Reid Kleckner2010-07-22
| | | | | | | Patch by Olivier Meurant! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109080 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-10
| | | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman2010-07-09
| | | | | | | a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman2010-07-08
| | | | | | | Debug info intrinsics win for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement bottom-up fast-isel. This has the advantage of not requiringDan Gohman2010-07-07
| | | | | | | a separate DCE pass over MachineInstrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107804 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily disable on-demand fast-isel.Dan Gohman2010-07-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107393 91177308-0d34-0410-b5e6-96231b3b80d8
* Fast isel no longer needs DeadMachineInstrElim to clean up after it.Dan Gohman2010-07-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107381 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some comments.Dan Gohman2010-06-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106809 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a -regalloc=default option that chooses a register allocator based on the -OJakob Stoklund Olesen2010-05-27
| | | | | | | | | optimization level. This only really affects llc for now because both the llvm-gcc and clang front ends override the default register allocator. I intend to remove that code later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104904 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Add TargetMachine support for setting the value of MCRelaxAll withDaniel Dunbar2010-05-26
| | | | | | -filetype=obj. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104747 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches.Daniel Dunbar2010-05-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104463 91177308-0d34-0410-b5e6-96231b3b80d8
* llc (et al): Add support for --show-encoding and --show-inst.Daniel Dunbar2010-05-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104029 91177308-0d34-0410-b5e6-96231b3b80d8
* XFAIL the test I added with vg_leak, apparently it is the first and only llcDaniel Dunbar2010-05-14
| | | | | | | -filetype=obj test, and -filetype=obj leaks a few objects. Added a FIXME, we need to sort out the ownership model for the various MC objects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103769 91177308-0d34-0410-b5e6-96231b3b80d8
* Code that needs a TargetMachine should have access to one directly, ratherDan Gohman2010-04-19
| | | | | | | than just getting one through a TargetLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101802 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix codegen passes. -disable-ssc shouldn't disable postra machine licm.Evan Cheng2010-04-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101622 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable post regalloc machine licm by default.Evan Cheng2010-04-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101023 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove late ARM codegen optimization pass committed by accident.Anton Korobeynikov2010-04-07
| | | | | | It is not ready for public yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100673 91177308-0d34-0410-b5e6-96231b3b80d8
* Add hook to insert late LLVM=>LLVM passes just before iselAnton Korobeynikov2010-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100640 91177308-0d34-0410-b5e6-96231b3b80d8
* Post regalloc LICM. Work in progress.Evan Cheng2010-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100592 91177308-0d34-0410-b5e6-96231b3b80d8
* Momentous day: remove the "O" member from AsmPrinter. Now all Chris Lattner2010-04-04
| | | | | | | | | | | "asm printering" happens through MCStreamer. This also Streamerizes PIC16 debug info, which escaped my attention. This removes a leak from LLVMTargetMachine of the 'legacy' output stream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100327 91177308-0d34-0410-b5e6-96231b3b80d8
* fix an ugly wart in the MCInstPrinter api where theChris Lattner2010-04-04
| | | | | | | | | raw_ostream to print an instruction to had to be specified at MCInstPrinter construction time instead of being able to pick at each call to printInstruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100307 91177308-0d34-0410-b5e6-96231b3b80d8
* rearrange MCContext ownership. Before LLVMTargetMachine created it Chris Lattner2010-03-13
| | | | | | | | | | | | | and passing off ownership to AsmPrinter. Now MachineModuleInfo creates it and owns it by value. This allows us to use MCSymbols more consistently throughout the rest of the code generator, and simplifies a bit of code. This also allows MachineFunction to keep an MCContext reference handy, and cleans up the TargetRegistry interfaces for AsmPrinters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98450 91177308-0d34-0410-b5e6-96231b3b80d8
* make the mangler take an MCContext instead of an MAI.Chris Lattner2010-03-12
| | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98363 91177308-0d34-0410-b5e6-96231b3b80d8
* remove MAI argument from createAsmStreamer since itChris Lattner2010-03-12
| | | | | | | can get it from the context now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98361 91177308-0d34-0410-b5e6-96231b3b80d8
* change MCContext to always have an MCAsmInfo.Chris Lattner2010-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98293 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Provide MCAssembler with a TargetAsmBackend.Daniel Dunbar2010-03-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98222 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable machine cse pass.Evan Cheng2010-03-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98132 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert accidental commit.Evan Cheng2010-03-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98045 91177308-0d34-0410-b5e6-96231b3b80d8
* - Make the machine cse dumb coalescer (as opposed to the more awesome simpleEvan Cheng2010-03-09
| | | | | | | | | | coalescer) handle sub-register classes. - Add heuristics to avoid non-profitable cse. Given the current lack of live range splitting, avoid cse when an expression has PHI use and the would be new use is in a BB where the expression wasn't already being used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98043 91177308-0d34-0410-b5e6-96231b3b80d8
* We don't really care about correct register liveness information after theJakob Stoklund Olesen2010-03-05
| | | | | | post-ra scheduler has run. Disable the verifier checks that late in the game. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97837 91177308-0d34-0410-b5e6-96231b3b80d8
* Run machine licm before machine cse to avoid messing up licm opportunities.Evan Cheng2010-03-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97752 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename -machine-cse to -enable-machine-cse.Evan Cheng2010-03-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97713 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an option to enable machine cse (it's not doing anything yet.Evan Cheng2010-03-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97627 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a flag to addPassesToEmit* to disable the Verifier pass runDan Gohman2010-02-28
| | | | | | | after LSR, so that clients can opt in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97357 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused "NoPRE" parameter in GVN and createGVNPass().Bob Wilson2010-02-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97235 91177308-0d34-0410-b5e6-96231b3b80d8
* Besides removing phi cycles that reduce to a single value, also remove deadBob Wilson2010-02-13
| | | | | | | | | phi cycles. Adjust a few tests to keep dead instructions from being optimized away. This (together with my previous change for phi cycles) fixes Apple radar 7627077. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96057 91177308-0d34-0410-b5e6-96231b3b80d8
* give MCCodeEmitters access to the current MCContext.Chris Lattner2010-02-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96038 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply the new LoopStrengthReduction code, with compile time andDan Gohman2010-02-12
| | | | | | | | | | | bug fixes, and with improved heuristics for analyzing foreign-loop addrecs. This change also flattens IVUsers, eliminating the stride-oriented groupings, which makes it easier to work with. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95975 91177308-0d34-0410-b5e6-96231b3b80d8
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