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path: root/lib/CodeGen/MachineLICM.cpp
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* Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. ↵Evan Cheng2011-09-01
| | | | | | Sorry, I can't come up with a small test case. rdar://10043690 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138934 91177308-0d34-0410-b5e6-96231b3b80d8
* Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng2011-06-29
| | | | | | MCInstrItineraries) into MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134049 91177308-0d34-0410-b5e6-96231b3b80d8
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-28
| | | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
* Look pass copies when determining whether hoisting would end up inserting ↵Evan Cheng2011-04-11
| | | | | | more copies. rdar://9266679 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129297 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich2011-03-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
* Sorry, several patches in one.Evan Cheng2011-01-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-10
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a FIXME comment.Dan Gohman2010-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118803 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineLICM should not claim to be preserving the CFG when it can split criticalJakob Stoklund Olesen2010-11-01
| | | | | | edges on demand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117982 91177308-0d34-0410-b5e6-96231b3b80d8
* Use instruction itinerary to determine what instructions are 'cheap'.Evan Cheng2010-10-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117348 91177308-0d34-0410-b5e6-96231b3b80d8
* More accurate estimate / tracking of register pressure.Evan Cheng2010-10-20
| | | | | | | | | | | - Initial register pressure in the loop should be all the live defs into the loop. Not just those from loop preheader which is often empty. - When an instruction is hoisted, update register pressure from loop preheader to the original BB. - Treat only use of a virtual register as kill since the code is still SSA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116956 91177308-0d34-0410-b5e6-96231b3b80d8
* Make CodeGen TBAA-aware.Dan Gohman2010-10-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116890 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-enable register pressure aware machine licm with fixes. Hoist() may haveEvan Cheng2010-10-19
| | | | | | | | erased the instruction during LICM so UpdateRegPressureAfter() should not reference it afterwards. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116845 91177308-0d34-0410-b5e6-96231b3b80d8
* Get rid of static constructors for pass registration. Instead, every pass ↵Owen Anderson2010-10-19
| | | | | | | | | | | | | | | | | | exposes an initializeMyPassFunction(), which must be called in the pass's constructor. This function uses static dependency declarations to recursively initialize the pass's dependencies. Clients that only create passes through the createFooPass() APIs will require no changes. Clients that want to use the CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h before parsing commandline arguments. I have tested this with all standard configurations of clang and llvm-gcc on Darwin. It is possible that there are problems with the static dependencies that will only be visible with non-standard options. If you encounter any crash in pass registration/creation, please send the testcase to me directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116820 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r116781 "- Add a hook for target to determine whether an instruction defDaniel Dunbar2010-10-19
| | | | | | is", which breaks some nightly tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116816 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for machine licm assert: RCCost <= RegPressure[RCId]Andrew Trick2010-10-19
| | | | | | | | in MultiSource/Benchmarks/VersaBench/beamformer/beamformer. SmallSet.insert returns true if the element is inserted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116790 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add a hook for target to determine whether an instruction def isEvan Cheng2010-10-19
| | | | | | | | | | | | "long latency" enough to hoist even if it may increase spilling. Reloading a value from spill slot is often cheaper than performing an expensive computation in the loop. For X86, that means machine LICM will hoist SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON instructions. - Enable register pressure aware machine LICM by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116781 91177308-0d34-0410-b5e6-96231b3b80d8
* More machine LICM work. It now tracks register pressure for path from ↵Evan Cheng2010-10-16
| | | | | | preheader to current BB and use the information determine whether hoisting is worthwhile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116654 91177308-0d34-0410-b5e6-96231b3b80d8
* Register pressure and instruction latency aware machine LICM. Work in progress.Evan Cheng2010-10-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116465 91177308-0d34-0410-b5e6-96231b3b80d8
* Begin adding static dependence information to passes, which will allow us toOwen Anderson2010-10-12
| | | | | | | | | | perform initialization without static constructors AND without explicit initialization by the client. For the moment, passes are required to initialize both their (potential) dependencies and any passes they preserve. I hope to be able to relax the latter requirement in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116334 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't waste time unfolding simple loads. The unfolded copy won't be hoisted.Evan Cheng2010-10-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116081 91177308-0d34-0410-b5e6-96231b3b80d8
* Now with fewer extraneous semicolons!Owen Anderson2010-10-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115996 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r110396 to fix buildbots.Owen Anderson2010-08-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-05
| | | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
* Comment typo.Dale Johannesen2010-07-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109765 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix batch of converting RegisterPass<> to INTIALIZE_PASS().Owen Anderson2010-07-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109045 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test for switch statements and increaseDale Johannesen2010-07-20
| | | | | | | | threshold a bit per experimentation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108935 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't hoist things out of a large switch inside aDale Johannesen2010-07-20
| | | | | | | | | | | | loop, for the reasons in the comments. This is a major win on 253.perlbmk on ARM Darwin. I expect it to be a good heuristic in general, but it's possible some things will regress; I'll be watching. 7940152. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108792 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach ProcessImplicitDefs to transform more COPY instructions into ↵Evan Cheng2010-07-14
| | | | | | IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108304 91177308-0d34-0410-b5e6-96231b3b80d8
* change machinelicm to use MachineInstr::isSafeToMove. NoChris Lattner2010-07-12
| | | | | | | | | intended functionality change. The avoidance of hoistiing implicitdef seems wrong though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108109 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix MachineLICM to actually visit inner loops.Dan Gohman2010-07-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108001 91177308-0d34-0410-b5e6-96231b3b80d8
* Move PHIElimination's SplitCriticalEdge for MachineBasicBlocks outDan Gohman2010-06-22
| | | | | | | | into a utility routine, teach it how to update MachineLoopInfo, and make use of it in MachineLICM to split critical edges on demand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106555 91177308-0d34-0410-b5e6-96231b3b80d8
* Doh. Machine LICM is re-initializing the CSE map over and over. Patch by ↵Evan Cheng2010-05-29
| | | | | | Anna Zaks. rdar://8037934. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105065 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach MachineLICM and MachineSink how to clear kill flags conservativelyDan Gohman2010-05-13
| | | | | | | when they move instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103737 91177308-0d34-0410-b5e6-96231b3b80d8
* When MachineLICM is hoisting a physical register after regalloc, make sure theJakob Stoklund Olesen2010-04-20
| | | | | | | | | | | register is not killed in the loop. This fixes 188.ammp on ARM where the post-ra scheduler would grab a register that looked available but wasn't. A testcase would be huge and fragile, sorry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101930 91177308-0d34-0410-b5e6-96231b3b80d8
* Postra machine licm must add registers defined by loop invariants to *all* ofEvan Cheng2010-04-17
| | | | | | | | | the live-in sets of BBs in the loop. Otherwise later pass may end up using the registers and override the invariant. rdar://7852937 No reasonablly sized test case possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101626 91177308-0d34-0410-b5e6-96231b3b80d8
* Fast path implicit_def check.Evan Cheng2010-04-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101183 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid variable shadowing.Evan Cheng2010-04-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101170 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand postra machine licm's capability a little more. If an instruction's ↵Evan Cheng2010-04-13
| | | | | | register operands are all loop invariants, then it's safe to hoist it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101167 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach postra machine licm to hoist more obvious invariants, e.g. ↵Evan Cheng2010-04-13
| | | | | | instructions with no source operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101154 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate MachineBasicBlock::const_livein_iterator and makeDan Gohman2010-04-13
| | | | | | | | | MachineBasicBlock::livein_iterator a const_iterator, because clients shouldn't ever be using the iterator interface to mutate the livein set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101147 91177308-0d34-0410-b5e6-96231b3b80d8
* Plug trivial leak.Benjamin Kramer2010-04-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101034 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete this obsolete comment.Dan Gohman2010-04-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100858 91177308-0d34-0410-b5e6-96231b3b80d8
* Make post regalloc machine licm functional. It now passes all of MultiSource.Evan Cheng2010-04-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100742 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comments for missed opportunities.Evan Cheng2010-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100610 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo.Evan Cheng2010-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100609 91177308-0d34-0410-b5e6-96231b3b80d8
* Post regalloc LICM. Work in progress.Evan Cheng2010-04-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100592 91177308-0d34-0410-b5e6-96231b3b80d8
* - Change MachineInstr::isIdenticalTo to take a new option that determines ↵Evan Cheng2010-03-03
| | | | | | | | | whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. - Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97628 91177308-0d34-0410-b5e6-96231b3b80d8
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