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path: root/lib/CodeGen/MachineRegisterInfo.cpp
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* Also inflate register classes around inline asm.Jakob Stoklund Olesen2011-10-12
| | | | | | | | | | Now that MI->getRegClassConstraint() can also handle inline assembly, don't bail when recomputing the register class of a virtual register used by inline asm. This fixes PR11078. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141836 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getCommonSubClass() into TRI.Jakob Stoklund Olesen2011-09-30
| | | | | | It will soon need the context. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140896 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a MinNumRegs argument to MRI::constrainRegClass().Jakob Stoklund Olesen2011-09-22
| | | | | | | | | | | The function will refuse to use a register class with fewer registers than MinNumRegs. This can be used by clients to avoid accidentally increase register pressure too much. The default value of MinNumRegs=0 doesn't affect how constrainRegClass() works. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140339 91177308-0d34-0410-b5e6-96231b3b80d8
* Move CalculateRegClass to MRI::recomputeRegClass.Jakob Stoklund Olesen2011-08-09
| | | | | | | | This function doesn't have anything to do with spill weights, and MRI already has functions for manipulating the register class of a virtual register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137123 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an isSSA() flag to MachineRegisterInfo.Jakob Stoklund Olesen2011-07-29
| | | | | | | | | | | | | This flag is true from isel to register allocation when the machine function is required to be in SSA form. The TwoAddressInstructionPass and PHIElimination passes clear the flag. The SSA flag wil be used by the machine code verifier to check for SSA form, and eventually an assertion can enforce it in +Asserts builds. This will catch the common target error of creating machine code with multiple defs of a virtual register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136532 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove RegClass2VRegMap from MachineRegisterInfo.Evan Cheng2011-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133967 91177308-0d34-0410-b5e6-96231b3b80d8
* Make it possible to have unallocatable register classes.Jakob Stoklund Olesen2011-06-02
| | | | | | | | | | | | | | | Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r124611 - "Keep track of incoming argument's location while emitting ↵Devang Patel2011-02-21
| | | | | | | | | | | | | LiveIns." In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body. This requires some coordination with debugger to get this working. - The debugger needs to be aware of prolog_end attribute attached with line table entries. - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126155 91177308-0d34-0410-b5e6-96231b3b80d8
* Keep track of incoming argument's location while emitting LiveIns.Devang Patel2011-01-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124611 91177308-0d34-0410-b5e6-96231b3b80d8
* Use IndexedMap for MachineRegisterInfo as well. No functional change.Jakob Stoklund Olesen2011-01-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123106 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.Jakob Stoklund Olesen2010-10-06
| | | | | | | | This function is intended to be used when inserting a machine instruction that trivially restricts the legal registers, like LEA requiring a GR32_NOSP argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115875 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.Jakob Stoklund Olesen2010-07-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108062 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach EmitLiveInCopies to omit copies for unused virtual registers,Dan Gohman2010-06-24
| | | | | | | and to clean up unused incoming physregs from the live-in list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106805 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't leak RegClass2VRegMap, which is now a new[] array instead of aDan Gohman2010-06-18
| | | | | | | std::vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106298 91177308-0d34-0410-b5e6-96231b3b80d8
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-18
| | | | | | | | MachineRegisterInfo doesn't have to confusingly allocate an extra entry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused function.Benjamin Kramer2010-05-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105100 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove schedule-livein-copies. It's not being used.Evan Cheng2010-05-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105095 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid adding duplicate function live-in's.Evan Cheng2010-05-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104560 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a utility function for conservatively clearing kill flags, and makeDan Gohman2010-05-13
| | | | | | | use of it in MachineCSE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103726 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence warningJakob Stoklund Olesen2010-05-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103508 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify the tracking of used physregs to a bulk bitor followed by a transitiveJakob Stoklund Olesen2010-05-11
| | | | | | | | closure after allocating all blocks. Add a few more test cases for -regalloc=fast. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103500 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-06
| | | | | | | doesn't have to guess. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace r102368 with code that's less fragile. This creates DBG_VALUE ↵Evan Cheng2010-04-28
| | | | | | instructions for function arguments early and insert them after instruction selection is done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102554 91177308-0d34-0410-b5e6-96231b3b80d8
* Insert dbg_value instructions for function entry block liveins (i.e. ↵Evan Cheng2010-04-26
| | | | | | function arguments). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102368 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the code for initialing the entry block livein set out ofDan Gohman2010-04-14
| | | | | | | SelectionDAGISel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101258 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the code for emitting livein copies out of SelectionDAGISel.Dan Gohman2010-04-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101254 91177308-0d34-0410-b5e6-96231b3b80d8
* Move MachineRegisterInfo's isLiveIn and isLiveOut out of line.Dan Gohman2010-04-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101145 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MachineRegisterInfo::hasOneUse and hasOneNonDBGUse.Evan Cheng2010-03-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97663 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify a few more uses of reg_iterator.Dan Gohman2009-09-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82812 91177308-0d34-0410-b5e6-96231b3b80d8
* Part 1.Evan Cheng2009-06-15
| | | | | | | | | | | | | | | | | | | | | | - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
* Move register allocation preference (or hint) from LiveInterval to ↵Evan Cheng2009-06-14
| | | | | | MachineRegisterInfo. This allows more passes to set them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73346 91177308-0d34-0410-b5e6-96231b3b80d8
* Move MachineRegisterInfo::setRegClass out of line.Dan Gohman2009-04-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69126 91177308-0d34-0410-b5e6-96231b3b80d8
* Move createVirtualRegister out-of-line.Dan Gohman2008-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60684 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a register class -> virtual registers map.Evan Cheng2008-10-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57844 91177308-0d34-0410-b5e6-96231b3b80d8
* Assert that all MachineInstrs update PhysRegUseDefLists inDan Gohman2008-07-07
| | | | | | | their cleanup code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53194 91177308-0d34-0410-b5e6-96231b3b80d8
* Added debugging routine dumpUses.Evan Cheng2008-02-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47042 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
* switch the register iterator to act more like hte LLVM value iterator: ↵Chris Lattner2008-01-01
| | | | | | | | | | | | dereferencing it now returns the machineinstr of the use. To get the operand, use I.getOperand(). Add a new MachineRegisterInfo::replaceRegWith, which is basically like Value::replaceAllUsesWith. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45482 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a trivial but handy function to efficiently return the machine Chris Lattner2008-01-01
| | | | | | | instruction that defines the specified vreg. Crazy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45480 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement automatically updated def/use lists for all MachineInstr register Chris Lattner2008-01-01
| | | | | | | | operands. The lists are currently kept in MachineRegisterInfo, but it does not yet provide an iterator interface to them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45477 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-31
that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
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