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path: root/lib/CodeGen/MachineScheduler.cpp
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* Silence GCC warning about falling off the end of a non-void function.Benjamin Kramer2012-11-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167618 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Heuristics based on the machine model.Andrew Trick2012-11-07
| | | | | | | | | | | | | | misched is disabled by default. With -enable-misched, these heuristics balance the schedule to simultaneously avoid saturating processor resources, expose ILP, and minimize register pressure. I've been analyzing the performance of these heuristics on everything in the llvm test suite in addition to a few other benchmarks. I would like each heuristic check to be verified by a unit test, but I'm still trying to figure out the best way to do that. The heuristics are still in considerable flux, but as they are refined we should be rigorous about unit testing the improvements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167527 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Rename RemainingCount to avoid confusion with remaining resources.Andrew Trick2012-11-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167443 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Added handleMove support for updating all kill flags, not just for ↵Andrew Trick2012-10-16
| | | | | | | | | allocatable regs. This is a medium term workaround until we have a more robust solution in the form of a register liveness utility for postRA passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166001 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: ILP scheduler for experimental heuristics.Andrew Trick2012-10-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165950 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-10
| | | | | | | | Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: avoid scheduling an instruction twice.Andrew Trick2012-10-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165416 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: add a hook for custom DAG postprocessing.Andrew Trick2012-09-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163915 91177308-0d34-0410-b5e6-96231b3b80d8
* Release build: guard dump functions withManman Ren2012-09-11
| | | | | | | | | "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)" No functional change. Update r163339. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163653 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorganize MachineScheduler interfaces and publish them in the header.Andrew Trick2012-09-11
| | | | | | | | | | | | | | The Hexagon target decided to use a lot of functionality from the target-independent scheduler. That's fine, and other targets should be able to do the same. This reorg and API update makes that easy. For the record, ScheduleDAGMI was not meant to be subclassed. Instead, new scheduling algorithms should be able to implement MachineSchedStrategy and be done. But if need be, it's nice to be able to extend ScheduleDAGMI, so I also made that easier. The target scheduler is somewhat more apt to break that way though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163580 91177308-0d34-0410-b5e6-96231b3b80d8
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-06
| | | | | | | No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163339 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify the computeOperandLatency API.Andrew Trick2012-08-23
| | | | | | | | | The logic for recomputing latency based on a ScheduleDAG edge was shady. This bypasses the problem by requiring the client to provide operand indices. This ensures consistent use of the machine model's API. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162420 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-22
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162347 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo (the the => the)Sylvestre Ledru2012-07-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-07
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: allow NULL InstrItineraries.Andrew Trick2012-07-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159599 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: avoid scheduling instructions that can't be dispatched.Andrew Trick2012-06-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159408 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: count micro-ops toward the issue limit.Andrew Trick2012-06-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159407 91177308-0d34-0410-b5e6-96231b3b80d8
* Guard private fields that are unused in Release builds with #ifndef NDEBUG.Benjamin Kramer2012-06-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158608 91177308-0d34-0410-b5e6-96231b3b80d8
* Move RegisterClassInfo.h.Andrew Trick2012-06-06
| | | | | | | Allow targets to access this API. It's required for RegisterPressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158102 91177308-0d34-0410-b5e6-96231b3b80d8
* Move RegisterPressure.h.Andrew Trick2012-06-06
| | | | | | | Make it a general utility for use by Targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158097 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-05
| | | | | | | Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: comments from code review.Andrew Trick2012-06-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157975 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: trace formattingAndrew Trick2012-05-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157455 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence unused variable warnings from when assertions are disabled.Kaelyn Uhrain2012-05-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157438 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Use the same scheduling heuristics with -misched-topdown/bottomup.Andrew Trick2012-05-24
| | | | | | (except the part about choosing direction) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157437 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Trace regpressure.Andrew Trick2012-05-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157429 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Give each ReadyQ a unique IDAndrew Trick2012-05-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157428 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Added ScoreboardHazardRecognizer.Andrew Trick2012-05-24
| | | | | | | | | | | | | | | | | | | The Hazard checker implements in-order contraints, or interlocked resources. Ready instructions with hazards do not enter the available queue and are not visible to other heuristics. The major code change is the addition of SchedBoundary to encapsulate the state at the top or bottom of the schedule, including both a pending and available queue. The scheduler now counts cycles in sync with the hazard checker. These are minimum cycle counts based on known hazards. Targets with no itinerary (x86_64) currently remain at cycle 0. To fix this, we need to provide some maximum issue width for all targets. We also need to add the concept of expected latency vs. minimum latency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157427 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Release bottom roots in reverse order.Andrew Trick2012-05-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157426 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: rename ReadyQ classAndrew Trick2012-05-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157425 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: copy comments so compareRPDelta is readable by itself.Andrew Trick2012-05-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157424 91177308-0d34-0410-b5e6-96231b3b80d8
* commentsAndrew Trick2012-05-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157020 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: trace ReadyQ.Andrew Trick2012-05-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157007 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Added 3-level regpressure back-off.Andrew Trick2012-05-17
| | | | | | | | | | | | | | | | | | | Introduce the basic strategy for register pressure scheduling. 1) Respect target limits at all times. 2) Indentify critical register classes (pressure sets). Track pressure within the scheduled region. Avoid increasing scheduled pressure for critical registers. 3) Avoid exceeding the max pressure of the region prior to scheduling. Added logic for picking between the top and bottom ready Q's based on regpressure heuristics. Status: functional but needs to be asjusted to achieve good results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157006 91177308-0d34-0410-b5e6-96231b3b80d8
* commentAndrew Trick2012-05-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157005 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: fix liveness iteratorsAndrew Trick2012-05-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157003 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Print machineinstrs with -debug-only=mischedAndrew Trick2012-05-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156576 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: tracing register pressure heuristics.Andrew Trick2012-05-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156575 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Add register pressure backoff to ConvergingScheduler.Andrew Trick2012-05-10
| | | | | | | | | | | | Prioritize the instruction that comes closest to keeping pressure under the target's limit. Then prioritize instructions that avoid increasing the max pressure in the scheduled region. The max pressure heuristic is a tad aggressive. Later I'll fix it to consider the unscheduled pressure as well. WIP: This is mostly functional but untested and not likely to do much good yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156574 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Release only unscheduled nodes into ReadyQ.Andrew Trick2012-05-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156573 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Added ReadyQ container wrapper for Top and Bottom Queues.Andrew Trick2012-05-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156572 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Introducing Top and Bottom register pressure trackers during ↵Andrew Trick2012-05-10
| | | | | | scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156571 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a naughty header include that breaks "installed" builds.Andrew Trick2012-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155486 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: try (not too hard) to place debug values where they belongAndrew Trick2012-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155458 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: ignore debug values during schedulingAndrew Trick2012-04-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155457 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: DAG builder support for tracking register pressure within the ↵Andrew Trick2012-04-24
| | | | | | | | | current scheduling region. The DAG builder is a convenient place to do it. Hopefully this is more efficient than a separate traversal over the same region. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155456 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: Add finalizeScheduler to complete the target interface.Andrew Trick2012-04-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153827 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: trace LiveIntervals after scheduling.Andrew Trick2012-03-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153161 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: obvious iterator update fixes for bottom-up.Andrew Trick2012-03-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153160 91177308-0d34-0410-b5e6-96231b3b80d8
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