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path: root/lib/CodeGen/MachineVerifier.cpp
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* [inline asm] Implement mayLoad and mayStore for inline assembly. In general,Chad Rosier2012-10-30
| | | | | | | | | | the MachineInstr MayLoad/MayLoad flags are based on the tablegen implementation. For inline assembly, however, we need to compute these based on the constraints. Revert r166929 as this is no longer needed, but leave the test case in place. rdar://12033048 and PR13504 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167040 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused BitVectors from getAllocatableSet().Jakob Stoklund Olesen2012-10-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165999 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-15
| | | | | | | Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165983 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop casting away const qualifier needlessly.Roman Divacky2012-09-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163258 91177308-0d34-0410-b5e6-96231b3b80d8
* Move tie checks into MachineVerifier::visitMachineOperand.Jakob Stoklund Olesen2012-09-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163152 91177308-0d34-0410-b5e6-96231b3b80d8
* Verify the consistency of inline asm operands.Jakob Stoklund Olesen2012-08-29
| | | | | | | | | | The operands on an INLINEASM machine instruction are divided into groups headed by immediate flag operands. Verify this structure. Extract verifyTiedOperands(), and only call it for non-inlineasm instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162849 91177308-0d34-0410-b5e6-96231b3b80d8
* Verify the tied operand flags.Jakob Stoklund Olesen2012-08-29
| | | | | | | | WHen running with -verify-machineinstrs, check that tied operands come in matching use/def pairs, and that they are consistent with MCInstrDesc when it applies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162816 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-22
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162347 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't add CFG edges for redundant conditional branches.Jakob Stoklund Olesen2012-08-20
| | | | | | | | | | | | | IR that hasn't been through SimplifyCFG can look like this: br i1 %b, label %r, label %r Make sure we don't create duplicate Machine CFG edges in this case. Fix the machine code verifier to accept conditional branches with a single CFG edge. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162230 91177308-0d34-0410-b5e6-96231b3b80d8
* Add CFG checks to MachineVerifier.Jakob Stoklund Olesen2012-08-20
| | | | | | | Verify that the predecessor and successor lists are consistent and free of duplicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162223 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix undefined behavior: don't perform array indexing through a potentially nullRichard Smith2012-08-15
| | | | | | | pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161919 91177308-0d34-0410-b5e6-96231b3b80d8
* Verify regunit intervals along with virtreg intervals.Jakob Stoklund Olesen2012-08-02
| | | | | | | Don't cause regunit intervals to be computed just to verify them. Only check the already cached intervals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161183 91177308-0d34-0410-b5e6-96231b3b80d8
* Add report() functions that take a LiveInterval argument.Jakob Stoklund Olesen2012-08-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161178 91177308-0d34-0410-b5e6-96231b3b80d8
* Extract some methods from verifyLiveIntervals.Jakob Stoklund Olesen2012-08-02
| | | | | | No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161149 91177308-0d34-0410-b5e6-96231b3b80d8
* Also verify RegUnit intervals at uses.Jakob Stoklund Olesen2012-08-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161147 91177308-0d34-0410-b5e6-96231b3b80d8
* Verify two-address constraints more carefully.Jakob Stoklund Olesen2012-07-25
| | | | | | Include <undef> operands and virtual registers after leaving SSA form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160734 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix crash in machine verifier when trying to print the def of a register ↵Pete Cooper2012-07-19
| | | | | | which has no def git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160531 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove tabs.Bill Wendling2012-07-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160475 91177308-0d34-0410-b5e6-96231b3b80d8
* Check for extra kill flags on live-out virtual registers.Jakob Stoklund Olesen2012-06-29
| | | | | | | This would previously get reported as the misleading "Virtual register def doesn't dominate all uses." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159460 91177308-0d34-0410-b5e6-96231b3b80d8
* Enforce stricter liveness rules for PHIs.Jakob Stoklund Olesen2012-06-25
| | | | | | | | | | | | | Verify that all paths from the entry block to a virtual register read pass through a def. Enable this check even when MRI->isSSA() is false. Verify that the live range of a virtual register is live out of all predecessor blocks, even for PHI-values. This requires that PHIElimination sometimes inserts IMPLICIT_DEF instruction in predecessor blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159150 91177308-0d34-0410-b5e6-96231b3b80d8
* Also verify the def index for early clobbers.Jakob Stoklund Olesen2012-06-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159039 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some more LiveInterval enumerations.Jakob Stoklund Olesen2012-06-20
| | | | | | Deterministically enumerate the virtual registers instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158872 91177308-0d34-0410-b5e6-96231b3b80d8
* Make machine verifier check the first instruction of the last bundle instead ofAkira Hatanaka2012-06-14
| | | | | | | | the last instruction of a basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158468 91177308-0d34-0410-b5e6-96231b3b80d8
* Move terminator machine verification to check ↵Pete Cooper2012-06-07
| | | | | | MachineBasicBlock::instr_iterator instead of MBB::iterator git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158154 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly verify liveness with bundled machine instructions.Jakob Stoklund Olesen2012-06-06
| | | | | | | | Bundles should be treated as one atomic transaction when checking liveness. That is how the register allocator (and VLIW targets) treats bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158116 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-01
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
* Optional def can be either a def or a use (of reg0).Evan Cheng2012-05-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157640 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a verifier bug.Jakob Stoklund Olesen2012-05-17
| | | | | | Make sure useless (def-only) intervals also get verified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157000 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-07
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable machine code verification after PreSched2 passes.Jakob Stoklund Olesen2012-03-28
| | | | | | | | | | The late scheduler depends on accurate liveness information if it is breaking anti-dependencies, so we should be able to verify it. Relax the terminator checking in the machine code verifier so it can handle the basic blocks created by if conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153614 91177308-0d34-0410-b5e6-96231b3b80d8
* Skip liveness verification when MRI->tracksLiveness() is false.Jakob Stoklund Olesen2012-03-28
| | | | | | | | | Extract the liveness verification into its own method. This makes it possible to run the machine code verifier after liveness information is no longer required to be valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153596 91177308-0d34-0410-b5e6-96231b3b80d8
* Report the defining instruction.Jakob Stoklund Olesen2012-03-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152460 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SSA verification to MachineVerifier.Jakob Stoklund Olesen2012-03-10
| | | | | | Somehow we never verified SSA dominance before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152458 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SmallPtrSet instead of DenseSet.Jakob Stoklund Olesen2012-03-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152457 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-05
| | | | | | static data size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the operand iterator into MachineInstrBundle.h where it belongs.Jakob Stoklund Olesen2012-02-29
| | | | | | | | | Extract a base class and provide four specific sub-classes for iterating over const/non-const bundles/instructions. This eliminates the mystery bool constructor argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151684 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle regmasks in the machine code verifier.Jakob Stoklund Olesen2012-02-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151607 91177308-0d34-0410-b5e6-96231b3b80d8
* Update machine code verifier.Jakob Stoklund Olesen2012-02-27
| | | | | | | | | After the SlotIndex slot names were updated, it is possible to apply stricter checks to live intervals. Also treat bundles as bags of operands when checking live intervals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151531 91177308-0d34-0410-b5e6-96231b3b80d8
* Update MachineVerifier to check the new physreg live-in rules.Lang Hames2012-02-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150496 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-14
| | | | | | | | | | | to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-07
| | | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove all remaining uses of Value::getNameStr().Benjamin Kramer2011-11-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144648 91177308-0d34-0410-b5e6-96231b3b80d8
* Use getVNInfoBefore() when it makes sense.Jakob Stoklund Olesen2011-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144517 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename SlotIndexes to match how they are used.Jakob Stoklund Olesen2011-11-13
| | | | | | | | | | | | | | | | | | | | The old naming scheme (load/use/def/store) can be traced back to an old linear scan article, but the names don't match how slots are actually used. The load and store slots are not needed after the deferred spill code insertion framework was deleted. The use and def slots don't make any sense because we are using half-open intervals as is customary in C code, but the names suggest closed intervals. In reality, these slots were used to distinguish early-clobber defs from normal defs. The new naming scheme also has 4 slots, but the names match how the slots are really used. This is a purely mechanical renaming, but some of the code makes a lot more sense now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144503 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix sub-register operand verification.Jakob Stoklund Olesen2011-10-05
| | | | | | | | | PhysReg operands are not allowed to have sub-register indices at all. For virtual registers with sub-reg indices, check that all registers in the register class support the sub-reg index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141220 91177308-0d34-0410-b5e6-96231b3b80d8
* Verify that terminators follow non-terminators.Jakob Stoklund Olesen2011-09-23
| | | | | | This exposes a -segmented-stacks bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140429 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick2011-09-21
| | | | | | | | | | | | | | This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop verifying hasPHIKill() flags.Jakob Stoklund Olesen2011-09-15
| | | | | | | | | | There is only one legitimate use remaining, in addIntervalsForSpills(). All other calls to hasPHIKill() are only used to update PHIKill flags. The addIntervalsForSpills() function is part of the old spilling framework, only used by linearscan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139783 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Don't check liveness of unallocatable registers."Jakob Stoklund Olesen2011-07-30
| | | | | | | The ARM target depends on CPSR liveness being tracked after register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136548 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't check liveness of unallocatable registers.Jakob Stoklund Olesen2011-07-29
| | | | | | | | | | | | This includes registers like EFLAGS and ST0-ST7. We don't check for liveness issues in the verifier and scavenger because registers will never be allocated from these classes. While in SSA form, we do care about the liveness of unallocatable unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for MachineDCE and MachineSinking. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136541 91177308-0d34-0410-b5e6-96231b3b80d8
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