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path: root/lib/CodeGen/PostRASchedulerList.cpp
Commit message (Expand)AuthorAge
* After PostRA scheduling, don't set kill flags on undef operands.Andrew Trick2013-10-16
* mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr c...Andrew Trick2013-08-23
* Simplify logic now that r182490 is in place. No functional change intended.Chad Rosier2013-05-22
* Remove special-casing of return blocks for liveness.Jakob Stoklund Olesen2013-02-05
* Use MachineInstrBuilder in a few CodeGen passes.Jakob Stoklund Olesen2012-12-20
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-03
* misched: Don't consider artificial edges weak edges.Andrew Trick2012-11-13
* misched: Infrastructure for weak DAG edges.Andrew Trick2012-11-12
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-15
* Release build: guard dump functions withManman Ren2012-09-11
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-06
* Add a getName function to MachineFunction. Use it in places that previously d...Craig Topper2012-08-22
* Move RegisterClassInfo.h.Andrew Trick2012-06-06
* Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer2012-06-06
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-01
* This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd2012-04-23
* misched interface: rename Begin/End to RegionBegin/RegionEnd since they are n...Andrew Trick2012-03-09
* misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick2012-03-07
* misched prep: rename InsertPos to End.Andrew Trick2012-03-07
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-07
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-07
* misched preparation: modularize schedule emission.Andrew Trick2012-03-07
* misched preparation: modularize schedule printing.Andrew Trick2012-03-07
* misched preparation: modularize schedule verification.Andrew Trick2012-03-07
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce stati...Craig Topper2012-03-05
* BitVectorize loop.Benjamin Kramer2012-02-23
* post-ra-sched: Turn the KillIndices vector into a bitvector, it only stored t...Benjamin Kramer2012-02-23
* post-ra-sched: Replace a std::set of regs with a bitvector.Benjamin Kramer2012-02-23
* Make calls scheduling boundaries post-ra.Jakob Stoklund Olesen2012-02-23
* Handle regmasks in FixupKills.Jakob Stoklund Olesen2012-02-23
* Make all pointers to TargetRegisterClass const since they are all pointers to...Craig Topper2012-02-22
* Codegen pass definition cleanup. No functionality.Andrew Trick2012-02-08
* Move pass configuration out of pass constructors: PostRAScheduler.Andrew Trick2012-02-08
* misched: Added ScheduleDAGInstrs::IsPostRAAndrew Trick2012-01-14
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-14
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-07
* Remove all remaining uses of Value::getNameStr().Benjamin Kramer2011-11-15
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-01
* Teach antidependency breakers to use RegisterClassInfo.Jakob Stoklund Olesen2011-06-16
* Update DBG_VALUEs while breaking anti dependencies.Devang Patel2011-06-02
* Add an issue width check to the postRA scheduler. Patch by Max Kazakov!Andrew Trick2011-06-01
* Typo: Reviewed by Alistair.Andrew Trick2011-05-06
* Post-RA scheduler compile time fix. Quadratic computation of DAG node depth.Andrew Trick2011-05-06
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-24
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-10
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-06
* Revert r110396 to fix buildbots.Owen Anderson2010-08-06
* Don't use PassInfo* as a type identifier for passes. Instead, use the addres...Owen Anderson2010-08-05
* Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister.Bill Wendling2010-07-15
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-18