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path: root/lib/CodeGen/ScheduleDAGInstrs.cpp
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* misched: Added CanHandleTerminators.Andrew Trick2012-04-13
* ScheduleDAGInstrs: When adding uses we add them into a set that's empty at th...Benjamin Kramer2012-03-16
* misched: add DAG edges from vreg defs to ExitSU.Andrew Trick2012-03-16
* misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick2012-03-14
* misched interface: rename Begin/End to RegionBegin/RegionEnd since they are n...Andrew Trick2012-03-09
* misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick2012-03-07
* misched prep: Comment the ScheduleDAGInstrs interface.Andrew Trick2012-03-07
* misched prep: Cleanup ScheduleDAGInstrs interface.Andrew Trick2012-03-07
* misched prep: rename InsertPos to End.Andrew Trick2012-03-07
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-07
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-07
* misched preparation: modularize schedule emission.Andrew Trick2012-03-07
* Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick2012-03-07
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-04
* PostRA sched: speed up physreg tracking by not abusing SparseSet.Andrew Trick2012-02-24
* misched: cleanup reaching def computationAndrew Trick2012-02-23
* PostRASched: Convert physreg def/use tracking to Jakob's SparseSet.Andrew Trick2012-02-23
* Don't compute latencies for regmask operands.Jakob Stoklund Olesen2012-02-22
* misched: Use SparseSet for VRegDegs for constant time clear().Andrew Trick2012-02-22
* Comment from code reviewAndrew Trick2012-02-22
* misched: DAG builder should not track dependencies for SSA defs.Andrew Trick2012-02-22
* Initialize SUnits before DAG building.Andrew Trick2012-02-22
* Clear virtual registers after they are no longer referenced.Andrew Trick2012-02-21
* misched: Initial code for building an MI level scheduling DAGAndrew Trick2012-01-14
* Move physreg dependency generation into aptly named addPhysRegDeps.Andrew Trick2012-01-14
* misched: Added ScheduleDAGInstrs::IsPostRAAndrew Trick2012-01-14
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-07
* Remove an unused variable.Chandler Carruth2012-01-05
* Minor postra scheduler cleanup. It could result in more precise antidependenc...Andrew Trick2012-01-05
* Model ARM predicated write as read-mod-write. e.g.Evan Cheng2011-12-14
* Allow target to specify register output dependency. Still default to one.Evan Cheng2011-12-14
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-14
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-07
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-06
* make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instr...Hal Finkel2011-12-02
* PostRA scheduler fix. Clear stale loop dependencies.Andrew Trick2011-10-07
* whitespaceAndrew Trick2011-10-07
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-01
* Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries)...Evan Cheng2011-06-29
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-28
* Remove dead code.Devang Patel2011-06-02
* Update DBG_VALUEs while breaking anti dependencies.Devang Patel2011-06-02
* During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALU...Devang Patel2011-06-02
* Added an assertion, and updated a comment.Andrew Trick2011-05-06
* ARM post RA scheduler compile time fix.Andrew Trick2011-05-05
* whitespaceAndrew Trick2011-05-05
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-15
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-07
* Move Value::getUnderlyingObject to be a standaloneDan Gohman2010-12-15
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-03