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path: root/lib/CodeGen/ScheduleDAGInstrs.cpp
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* misched: better alias analysis.Andrew Trick2012-11-28
* Fix indeterminism in MI scheduler DAG construction.Sergei Larin2012-11-15
* misched: Infrastructure for weak DAG edges.Andrew Trick2012-11-12
* ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.Andrew Trick2012-11-06
* [inline asm] Implement mayLoad and mayStore for inline assembly. In general,Chad Rosier2012-10-30
* This patch addresses a problem with the Post RA scheduler generating anPreston Gurd2012-10-29
* Fix typo in comment.Nick Lewycky2012-10-26
* misched: ILP scheduler for experimental heuristics.Andrew Trick2012-10-15
* misched: Use the TargetSchedModel interface wherever possible.Andrew Trick2012-10-10
* misched: Remove LoopDependencies heuristic.Andrew Trick2012-10-09
* misched: remove the unused getSpecialAddressLatency hook.Andrew Trick2012-10-08
* misched: remove forceUnitLatencies. Defaults are handled by the default Sched...Andrew Trick2012-10-08
* misched: Make ScheduleDAGInstrs use the TargetSchedule interface.Andrew Trick2012-09-18
* Release build: guard dump functions withManman Ren2012-09-11
* Release build: guard dump functions with "ifndef NDEBUG"Manman Ren2012-09-06
* Rename hasVolatileMemoryRef() to hasOrderedMemoryRef().Jakob Stoklund Olesen2012-08-29
* Simplify the computeOperandLatency API.Andrew Trick2012-08-23
* Use the latest MachineRegisterInfo APIs. No functionality.Andrew Trick2012-07-30
* Reenable a basic SSA DAG builder optimization.Andrew Trick2012-07-28
* misched: disable SSA check pending PR13112.Andrew Trick2012-06-14
* sched: fix latency of memory dependence chain edges for consistency.Andrew Trick2012-06-13
* Move RegisterPressure.h.Andrew Trick2012-06-06
* Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer2012-06-06
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-05
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-01
* Use LiveRangeQuery in ScheduleDAGInstrs.Jakob Stoklund Olesen2012-05-20
* Add -enable-aa-sched-mi, off by default, for AliasAnalysis inside MachineSche...Andrew Trick2012-05-15
* misched: DAG builder must special case earlyclobberAndrew Trick2012-04-24
* misched: DAG builder support for tracking register pressure within the curren...Andrew Trick2012-04-24
* New and improved comment.Andrew Trick2012-04-20
* SparseSet: Add support for key-derived indexes and arbitrary key types.Andrew Trick2012-04-20
* misched: initialize BBAndrew Trick2012-04-20
* misched: Added CanHandleTerminators.Andrew Trick2012-04-13
* ScheduleDAGInstrs: When adding uses we add them into a set that's empty at th...Benjamin Kramer2012-03-16
* misched: add DAG edges from vreg defs to ExitSU.Andrew Trick2012-03-16
* misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick2012-03-14
* misched interface: rename Begin/End to RegionBegin/RegionEnd since they are n...Andrew Trick2012-03-09
* misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick2012-03-07
* misched prep: Comment the ScheduleDAGInstrs interface.Andrew Trick2012-03-07
* misched prep: Cleanup ScheduleDAGInstrs interface.Andrew Trick2012-03-07
* misched prep: rename InsertPos to End.Andrew Trick2012-03-07
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-07
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-07
* misched preparation: modularize schedule emission.Andrew Trick2012-03-07
* Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick2012-03-07
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-04
* PostRA sched: speed up physreg tracking by not abusing SparseSet.Andrew Trick2012-02-24
* misched: cleanup reaching def computationAndrew Trick2012-02-23
* PostRASched: Convert physreg def/use tracking to Jakob's SparseSet.Andrew Trick2012-02-23
* Don't compute latencies for regmask operands.Jakob Stoklund Olesen2012-02-22