summaryrefslogtreecommitdiff
path: root/lib/CodeGen/ScheduleDAGInstrs.h
Commit message (Collapse)AuthorAge
* PostRA scheduler fix. Clear stale loop dependencies.Andrew Trick2011-10-07
| | | | | | | Fixes <rdar://problem/10235725> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141357 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2011-10-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141356 91177308-0d34-0410-b5e6-96231b3b80d8
* Update DBG_VALUEs while breaking anti dependencies.Devang Patel2011-06-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132487 91177308-0d34-0410-b5e6-96231b3b80d8
* During post RA scheduling, do not try to chase reg defs. to preserve ↵Devang Patel2011-06-02
| | | | | | | | | DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def. Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132483 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly model the latency of register defs which are 1) function returns orEvan Cheng2010-10-23
| | | | | | | | | | | | 2) live-outs. Previously the post-RA schedulers completely ignore these dependencies since returns, branches, etc. are all scheduling barriers. This patch model the latencies between instructions being scheduled and the barriers. It also handle calls by marking their register uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117193 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-10
| | | | | | | | | | | | take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
* Change ScheduleDAGInstrs::Defs and ::Uses to be variable-size vectorsBob Wilson2010-07-24
| | | | | | | | instead of fixed size arrays, so that increasing FirstVirtualRegister to 16K won't cause a compile time performance regression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109330 91177308-0d34-0410-b5e6-96231b3b80d8
* When processing loops for scheduling latencies (used for live outs on loopJim Grosbach2010-06-29
| | | | | | | back-edges), make sure not to include dbg_value instructions in the count. Closing in on the end of rdar://7797940 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107119 91177308-0d34-0410-b5e6-96231b3b80d8
* I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename itDuncan Sands2010-05-11
| | | | | | | | to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is the opposite, for future use by dragonegg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103495 91177308-0d34-0410-b5e6-96231b3b80d8
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-01
| | | | | | | changes before doing phi lowering for switches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
* Progress towards shepherding debug info through SelectionDAG.Dale Johannesen2010-03-10
| | | | | | | | | No functional effect yet. This is still evolving and should not be viewed as final. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98195 91177308-0d34-0410-b5e6-96231b3b80d8
* Spill slots cannot alias.Evan Cheng2009-10-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84432 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a redundant member variable.Dan Gohman2009-10-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83857 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman2009-10-09
| | | | | | | | | | | | | | | is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83687 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ↵Evan Cheng2009-09-18
| | | | | | | | | sdisel will use to properly complete phi nodes. Not functionality change yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82273 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the schedule itinerary operand use/def cycle information to adjust ↵David Goodwin2009-08-19
| | | | | | dependence edge latency for post-RA scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79425 91177308-0d34-0410-b5e6-96231b3b80d8
* When scheduling a block in parts, keep track of the overallDan Gohman2009-02-11
| | | | | | | | | | | | instruction index across each part. Instruction indices are used to make live range queries, and live ranges can extend beyond scheduling region boundaries. Refactor the ScheduleDAGSDNodes class some more so that it doesn't have to worry about this additional information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64288 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor out more code for computing register live-range informationforDan Gohman2009-02-10
| | | | | | | | | | | | scheduling, and generalize is so that preserves state across scheduling regions. This fixes incorrect live-range information around terminators and labels, which are effective region boundaries. In place of looking for terminators to anchor inter-block dependencies, introduce special entry and exit scheduling units for this purpose. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64254 91177308-0d34-0410-b5e6-96231b3b80d8
* Move ScheduleDAGInstrs.h to be a private header. Front-endsDan Gohman2009-02-06
that used this header to select a scheduling policy should use SchedulerRegistry.h instead (llvm-gcc and clang were updated a while ago). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63934 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-28 21:11:48 +0000