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path: root/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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* Merging r200201:Tom Stellard2014-04-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r200201 | stpworld | 2014-01-27 04:18:31 -0500 (Mon, 27 Jan 2014) | 31 lines Fix for PR18102. Issue outcomes from DAGCombiner::MergeConsequtiveStores, more precisely from mem-ops sequence sorting. Consider, how MergeConsequtiveStores works for next example: store i8 1, a[0] store i8 2, a[1] store i8 3, a[1] ; a[1] again. return ; DAG starts here 1. Method will collect all the 3 stores. 2. It sorts them by distance from the base pointer (farthest with highest index). 3. It takes first consecutive non-overlapping stores and (if possible) replaces them with a single store instruction. The point is, we can't determine here which 'store' instruction would be the second after sorting ('store 2' or 'store 3'). It happens that 'store 3' would be the second, and 'store 2' would be the third. So after merging we have the next result: store i16 (1 | 3 << 8), base ; is a[0] but bit-casted to i16 store i8 2, a[1] So actually we swapped 'store 3' and 'store 2' and got wrong contents in a[1]. Fix: In sort routine just also take into account mem-op sequence number. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205806 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r196858:Bill Wendling2013-12-10
| | | | | | | | | | | ------------------------------------------------------------------------ r196858 | nadav | 2013-12-09 17:13:59 -0800 (Mon, 09 Dec 2013) | 1 line Fix PR18162 - Incorrect assertion assumed that the SDValue resno is zero. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196886 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r191049 and r191059. They were causing failures. See PR17975.Bill Wendling2013-12-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196521 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195670:Bill Wendling2013-11-25
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195670 | void | 2013-11-25 10:05:22 -0800 (Mon, 25 Nov 2013) | 5 lines Unrevert r195599 with testcase fix. I'm not sure how it was checking for the wrong values... PR18023. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195672 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195636:Bill Wendling2013-11-25
| | | | | | | | | | | | ------------------------------------------------------------------------ r195636 | aemerson | 2013-11-25 03:24:18 -0800 (Mon, 25 Nov 2013) | 2 lines Revert r195599 as it broke the builds. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195671 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195635:Daniel Sanders2013-11-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195635 | dsanders | 2013-11-25 11:14:43 +0000 (Mon, 25 Nov 2013) | 19 lines Fixed tryFoldToZero() for vector types that need expansion. Summary: Moved the requirement for SelectionDAG::getConstant() to return legally typed nodes slightly earlier. There were two optional DAGCombine passes that were missed out and were required to produce type-legal DAGs. Simplified a code-path in tryFoldToZero() to use SelectionDAG::getConstant(). This provides support for both promoted and expanded vector types whereas the previous code only supported promoted vector types. Fixes a "Type for zero vector elements is not legal" assertion detected by an llvm-stress generated test. Reviewers: resistor CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2251 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195651 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195599:Bill Wendling2013-11-25
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r195599 | void | 2013-11-24 21:01:21 -0800 (Sun, 24 Nov 2013) | 4 lines Don't look past volatile loads. A volatile load should block us from trying to coalesce stores. PR18023 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195600 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195397:Bill Wendling2013-11-22
| | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195397 | tstellar | 2013-11-21 16:39:23 -0800 (Thu, 21 Nov 2013) | 11 lines Split SETCC if VSELECT requires splitting too. This patch is a rewrite of the original patch commited in r194542. Instead of relying on the type legalizer to do the splitting for us, we now peform the splitting ourselves in the DAG combiner. This is necessary for the case where the vector mask is a legal type after promotion and still wouldn't require splitting. Patch by: Juergen Ributzka NOTE: This is a candidate for the 3.4 branch. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195413 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: Partially revert r192795, getNOT was fixed not to create ↵Benjamin Kramer2013-11-17
| | | | | | illegal constants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194959 91177308-0d34-0410-b5e6-96231b3b80d8
* Add target hook to prevent folding some bitcasted loads.Matt Arsenault2013-11-15
| | | | | | | | | | | | | This is to avoid this transformation in some cases: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently casting the load to a smaller vector of larger types and loading is more efficient. Patch by Micah Villmow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194783 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.Juergen Ributzka2013-11-13
| | | | | | | | | | | | | | | | | | | | | | This patch reapplies r193676 with an additional fix for the Hexagon backend. The SystemZ backend has already been fixed by r194148. The Type Legalizer recognizes that VSELECT needs to be split, because the type is to wide for the given target. The same does not always apply to SETCC, because less space is required to encode the result of a comparison. As a result VSELECT is split and SETCC is unrolled into scalar comparisons. This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG Combiner. If a matching pattern is found, then the result mask of SETCC is promoted to the expected vector mask type for the given target. Now the type legalizer will split both VSELECT and SETCC. This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>. Reviewed by Nadav git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194542 91177308-0d34-0410-b5e6-96231b3b80d8
* Vector forms of SHL, SRA, and SRL can be constant folded using ↵Daniel Sanders2013-11-11
| | | | | | | | | | | | | | SimplifyVBinOp too Reviewers: dsanders Reviewed By: dsanders CC: llvm-commits, nadav Differential Revision: http://llvm-reviews.chandlerc.com/D1958 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194393 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs ↵Juergen Ributzka2013-10-30
| | | | | | | | splitting too." Now Hexagon and SystemZ are not happy with it :-( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193677 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.Juergen Ributzka2013-10-30
| | | | | | | | | | | | | | | | | | | | The Type Legalizer recognizes that VSELECT needs to be split, because the type is to wide for the given target. The same does not always apply to SETCC, because less space is required to encode the result of a comparison. As a result VSELECT is split and SETCC is unrolled into scalar comparisons. This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG Combiner. If a matching pattern is found, then the result mask of SETCC is promoted to the expected vector mask type for the given target. This mask has usually the same size as the VSELECT return type (except for Intel KNL). Now the type legalizer will split both VSELECT and SETCC. This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>. Reviewed by Nadav git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193676 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Respect volatility when checking for aliasesRichard Sandiford2013-10-28
| | | | | | | | | Making useAA() default to true for SystemZ showed that the combiner alias analysis wasn't handling volatile accesses. This hit many of the SystemZ tests, but I arbitrarily picked one for the purpose of this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193518 91177308-0d34-0410-b5e6-96231b3b80d8
* Keep TBAA info when rewriting SelectionDAG loads and storesRichard Sandiford2013-10-28
| | | | | | | | | | | | | | | | | | Most SelectionDAG code drops the TBAA info when creating a new form of a load and store (e.g. during legalization, or when converting a plain load to an extending one). This patch tries to catch all cases where the TBAA information can legitimately be carried over. The patch adds alternative forms of getLoad() and getExtLoad() that take a MachineMemOperand instead of individual fields. (The corresponding getTruncStore() already exists.) The idea is to use the MachineMemOperand forms when all fields are carried over (size, pointer info, isVolatile, isNonTemporal, alignment and TBAA info). If some adjustment is being made, e.g. to narrow the load, then we still pass the individual fields but also pass the TBAA info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193517 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize concat_vectors(X, undef) -> scalar_to_vector(X).Nadav Rotem2013-10-25
| | | | | | | | | This optimization is not SSE specific so I am moving it to DAGco. The new scalar_to_vector dag node exposed a missing pattern in the AArch64 target that I needed to add. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193393 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix edge condition in DAGCombiner to improve codegen of shift sequences.Andrea Di Biagio2013-10-17
| | | | | | | | | | | | | When canonicalizing dags according to the rule (shl (zext (shr X, c1) ), c1) ==> (zext (shl (shr X, c1), c1)) remember to add the new shl dag to the DAGCombiner worklist of nodes. If we don't explicitly add it to the worklist of nodes to visit, we may not trigger later on the rule that folds the shift left + logical shift right into a AND instruction with bitmask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192883 91177308-0d34-0410-b5e6-96231b3b80d8
* [projects/test-suite] White space and long line fixes.Jack Carter2013-10-17
| | | | | | | No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192863 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: Don't fold xor into not if getNOT would introduce an illegal ↵Benjamin Kramer2013-10-16
| | | | | | | | | | | constant. This happens e.g. with <2 x i64> -1 on x86_32. It cannot be generated directly because i64 is illegal. It would be nice if getNOT would handle this transparently, but I don't see a way to generate a legal constant there right now. Fixes PR17487. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192795 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Reapply load slicing (192471) with a test that explicitly set ↵Quentin Colombet2013-10-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sse4.2 support. This should fix the buildbots. Original commit message: [DAGCombiner] Slice a big load in two loads when the element are next to each other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192476 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Revert load slicing (r192471), until I figure out why it fails ↵Quentin Colombet2013-10-11
| | | | | | on ubuntu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192474 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Slice a big load in two loads when the element are next to eachQuentin Colombet2013-10-11
| | | | | | | | | | | | | | | | | | | | | | | | | other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192471 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix DAGCombiner::visitFP_EXTEND to ignore indexed loadsHal Finkel2013-10-04
| | | | | | | | | | | | | | | | DAGCombiner::visitFP_EXTEND will apply the following transformation: fold (fpext (load x)) -> (fpext (fptrunc (extload x))) but the implementation does not handle indexed loads (pre/post inc.), but did not specifically ignore them either (unlike for extending loads, which it already ignored), causing an assert when the transformation was applied to an indexed load. This is the minimal fix for correctness (causing the transformation to be skipped for indexed loads). Unfortunately, I don't have an in-tree test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191989 91177308-0d34-0410-b5e6-96231b3b80d8
* Added checking code whehter target supports specific dag combining about rotateJin-Gu Kang2013-10-03
| | | | | | | | | | | | | | | | | | | | | | | | or not. The corresponding dag patterns are as following: "DAGCombier::MatchRotate" function in DAGCombiner.cpp Pattern1 // fold (or (shl (*ext x), (*ext y)), // (srl (*ext x), (*ext (sub 32, y)))) -> // (*ext (rotl x, y)) // fold (or (shl (*ext x), (*ext y)), // (srl (*ext x), (*ext (sub 32, y)))) -> // (*ext (rotr x, (sub 32, y))) pattern2 // fold (or (shl (*ext x), (*ext (sub 32, y))), // (srl (*ext x), (*ext y))) -> // (*ext (rotl x, y)) // fold (or (shl (*ext x), (*ext (sub 32, y))), // (srl (*ext x), (*ext y))) -> // (*ext (rotr x, (sub 32, y))) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191905 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply the change from r191393 with fix for pr17380.Andrea Di Biagio2013-09-27
| | | | | | | | | | | This change fixes the problem reported in pr17380 and re-add the dagcombine transformation ensuring that the value types are always legal if the transformation is triggered after Legalization took place. Added the test case from pr17380. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191509 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r191393 since it caused pr17380.Andrea Di Biagio2013-09-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191438 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach DAGCombiner how to canonicalize dags according to the ruleAndrea Di Biagio2013-09-25
| | | | | | | | | | | | | (shl (zext (shr A, X)), X) => (zext (shl (shr A, X), X)). The rule only triggers when there are no other uses of the zext to avoid materializing more instructions. This helps the DAGCombiner understand that the shl/shr sequence can then be converted into an and instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191393 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: Unify rotate matching for extended and unextended amounts.Benjamin Kramer2013-09-24
| | | | | | No functionality change, lots of indentation changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191303 91177308-0d34-0410-b5e6-96231b3b80d8
* fix typo: than -> thenKay Tiong Khoo2013-09-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191214 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs ↵Juergen Ributzka2013-09-21
| | | | | | | | splitting too." This reverts commit r191130. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191138 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.Juergen Ributzka2013-09-21
| | | | | | | | | | | | | | | | | | The Type Legalizer recognizes that VSELECT needs to be split, because the type is to wide for the given target. The same does not always apply to SETCC, because less space is required to encode the result of a comparison. As a result VSELECT is split and SETCC is unrolled into scalar comparisons. This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG Combiner. If a matching pattern is found, then the result mask of SETCC is promoted to the expected vector mask for the given target. This mask has usually te same size as the VSELECT return type (except for Intel KNL). Now the type legalizer will split both VSELECT and SETCC. This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191130 91177308-0d34-0410-b5e6-96231b3b80d8
* Add braces to suppress Clang's dangling-else warning.David Blaikie2013-09-20
| | | | | | These violations were introduced in r191049 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191059 91177308-0d34-0410-b5e6-96231b3b80d8
* PR16726: extend rol/ror matchingKai Nacke2013-09-19
| | | | | | | | | | | | | | | | | | | | | | C-like languages promote types like unsigned short to unsigned int before performing an arithmetic operation. Currently the rotate matcher in the DAGCombiner does not consider this situation. This commit extends the DAGCombiner in the way that the pattern (or (shl ([az]ext x), (*ext y)), (srl ([az]ext x), (*ext (sub 32, y)))) is folded into ([az]ext (rotl x, y)) The matching is restricted to aext and zext because in this cases the upper bits are either undefined or known. Test case is included. This fixes PR16726. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191049 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert PR16726: extend rol/ror matchingKai Nacke2013-09-19
| | | | | | There is a buildbot failure. Need to investigate this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191048 91177308-0d34-0410-b5e6-96231b3b80d8
* PR16726: extend rol/ror matchingKai Nacke2013-09-19
| | | | | | | | | | | | | | | | | | | | | | C-like languages promote types like unsigned short to unsigned int before performing an arithmetic operation. Currently the rotate matcher in the DAGCombiner does not consider this situation. This commit extends the DAGCombiner in the way that the pattern (or (shl ([az]ext x), (*ext y)), (srl ([az]ext x), (*ext (sub 32, y)))) is folded into ([az]ext (rotl x, y)) The matching is restricted to aext and zext because in this cases the upper bits are either undefined or known. Test case is included. This fixes PR16726. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191045 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: Don't fold vector muls with constants that look like a splat of ↵Benjamin Kramer2013-09-19
| | | | | | | | a power of 2 but differ in bit width. PR17283. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191000 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent assert in CombinerGlobalAA with null valuesHal Finkel2013-09-15
| | | | | | | DAGCombiner::isAlias can be called with SrcValue1 or SrcValue2 null, and we can't use AA in this case (if we try, then the casting code in AA will assert). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190763 91177308-0d34-0410-b5e6-96231b3b80d8
* Use TargetSubtargetInfo::useAA() in DAGCombineHal Finkel2013-08-29
| | | | | | | This uses the TargetSubtargetInfo::useAA() function to control the defaults of the -combiner-alias-analysis and -combiner-global-alias-analysis options. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189564 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo and coding style of a previous commit. No functional change.Juergen Ributzka2013-08-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189526 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: make sure or/shl/srl really has zero high bits before forming bswapTim Northover2013-08-27
| | | | | | | | We want to convert code like (or (srl N, 8), (shl N, 8)) into (srl (bswap N), const), but this is only valid if the bits above 16 on the source pattern are 0, the checks we were doing on this were slightly wrong before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189348 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG: Remove unnecessary uses of TargetLowering::getPointerTy()Tom Stellard2013-08-26
| | | | | | | | | | | | If we have a binary operation like ISD:ADD, we can set the result type equal to the result type of one of its operands rather than using TargetLowering::getPointerTy(). Also, any use of DAG.getIntPtrConstant(C) as an operand for a binary operation can be replaced with: DAG.getConstant(C, OtherOperand.getValueType()); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189227 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach BaseIndexOffset::match to identify base pointers in loops.Juergen Ributzka2013-08-21
| | | | | | | | | | | | | | | The small utility function that pattern matches Base + Index + Offset patterns for loads and stores fails to recognize the base pointer for loads/stores from/into an array at offset 0 inside a loop. As a result DAGCombiner::MergeConsecutiveStores was not able to merge all stores. This commit fixes the issue by adding an additional pattern match and also a test case. Reviewer: Nadav git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188936 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace getValueType().getSimpleVT() with getSimpleValueType().Craig Topper2013-08-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188442 91177308-0d34-0410-b5e6-96231b3b80d8
* DAG: Combine (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)Jim Grosbach2013-08-13
| | | | | | | | | | | | | | | | | | | | | | | A common idiom is to use zero and all-ones as sentinal values and to check for both in a single conditional ("x != 0 && x != (unsigned)-1"). That generates code, for i32, like: testl %edi, %edi setne %al cmpl $-1, %edi setne %cl andb %al, %cl With this transform, we generate the simpler: incl %edi cmpl $1, %edi seta %al Similar improvements for other integer sizes and on other platforms. In general, combining the two setcc instructions into one is better. rdar://14689217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188315 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize mask generation for one of the DAG combiner shufflevector cases.Craig Topper2013-08-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187961 91177308-0d34-0410-b5e6-96231b3b80d8
* TargetLowering: Add getVectorIdxTy() function v2Tom Stellard2013-08-05
| | | | | | | | | | | | | | | | | | | | | This virtual function can be implemented by targets to specify the type to use for the index operand of INSERT_VECTOR_ELT, EXTRACT_VECTOR_ELT, INSERT_SUBVECTOR, EXTRACT_SUBVECTOR. The default implementation returns the result from TargetLowering::getPointerTy() The previous code was using TargetLowering::getPointerTy() for vector indices, because this is guaranteed to be legal on all targets. However, using TargetLowering::getPointerTy() can be a problem for targets with pointer sizes that differ across address spaces. On such targets, when vectors need to be loaded or stored to an address space other than the default 'zero' address space (which is the address space assumed by TargetLowering::getPointerTy()), having an index that is a different size than the pointer can lead to inefficient pointer calculations, (e.g. 64-bit adds for a 32-bit address space). There is no intended functionality change with this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187748 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] insert_vector_elt: Avoid building a vector twice.Quentin Colombet2013-07-30
| | | | | | | | | | | | | | | | | | This patch prevents the following combine when the input vector is used more than once. insert_vector_elt (build_vector elt0, ..., eltN), NewEltIdx, idx => build_vector elt0, ..., NewEltIdx, ..., eltN The reasons are: - Building a vector may be expensive, so try to reuse the existing part of a vector instead of creating a new one (think big vectors). - elt0 to eltN now have two users instead of one. This may prevent some other optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187396 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)FreeTom Stellard2013-07-23
| | | | | | | This commit also implements these functions for R600 and removes a test case that was relying on the buggy behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187007 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-14
| | | | | | size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
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