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path: root/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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* Don't use register classes larger than TLI->getRegClassFor(VT).Jakob Stoklund Olesen2011-06-16
| | | | | | | | | | In Thumb mode we cannot handle GPR virtual registers, even though some instructions can. When isel is lowering a CopyFromReg, it should limit itself to subclasses of getRegClassFor(VT). <rdar://problem/9624323> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133210 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the REG_SEQUENCE SDNode to take an explict register class ID as its ↵Owen Anderson2011-06-16
| | | | | | | | | first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change. This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133178 91177308-0d34-0410-b5e6-96231b3b80d8
* Use TRI::has{Sub,Super}ClassEq() where possible.Jakob Stoklund Olesen2011-06-02
| | | | | | No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132455 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-10
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-07
| | | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize:Evan Cheng2011-01-05
| | | | | | | | | | r1025 = s/zext r1024, 4 r1026 = extract_subreg r1025, 4 to: r1026 = copy r1024 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122925 91177308-0d34-0410-b5e6-96231b3b80d8
* flags -> glue for selectiondagChris Lattner2010-12-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122509 91177308-0d34-0410-b5e6-96231b3b80d8
* Change all self assignments X=X to (void)X, so that we can turn on aJeffrey Yasskin2010-12-23
| | | | | | | | | new gcc warning that complains on self-assignments and self-initializations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122458 91177308-0d34-0410-b5e6-96231b3b80d8
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-21
| | | | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.Bob Wilson2010-12-17
| | | | | | Radar 8776599 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122018 91177308-0d34-0410-b5e6-96231b3b80d8
* Reword comment slightly.Eric Christopher2010-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121293 91177308-0d34-0410-b5e6-96231b3b80d8
* Split pseudo-instruction expansion into a separate pass, to make itDan Gohman2010-11-16
| | | | | | | | easier to debug, and to avoid complications when the CFG changes in the middle of the instruction selection process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119382 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r112461. It was failing on PPC...Bill Wendling2010-08-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112463 91177308-0d34-0410-b5e6-96231b3b80d8
* When adding a register, we should mark it as "def" if it can optionally defineBill Wendling2010-08-30
| | | | | | | said (physical) register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112461 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit COPY instructions instead of using copyRegToReg in InstrEmitter,Jakob Stoklund Olesen2010-07-10
| | | | | | | | | ScheduleDAGEmit, TwoAddressLowering, and PHIElimination. This switches the bulk of register copies to using COPY, but many less used copyRegToReg calls remain. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108050 91177308-0d34-0410-b5e6-96231b3b80d8
* Insert IMPLICIT_DEF instructions at the current insert position, notDan Gohman2010-07-10
| | | | | | | at the end of the block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108045 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-10
| | | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman2010-07-09
| | | | | | | a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen2010-07-08
| | | | | | | | | EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman2010-07-08
| | | | | | | Debug info intrinsics win for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
* Not all custom inserters create new basic blocks. If the inserterDan Gohman2010-07-07
| | | | | | | didn't create a new block, don't reset the insert position. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107813 91177308-0d34-0410-b5e6-96231b3b80d8
* Update comment.Devang Patel2010-07-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107796 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r107655 with fixes; insert the pseudo instruction intoDan Gohman2010-07-06
| | | | | | | | the block before calling the expansion hook. And don't put EFLAGS in a mbb's live-in list twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate the AlignStack bit in InlineAsm's to the Dale Johannesen2010-07-02
| | | | | | | | | | | | | | | | | | | | | PrologEpilog code, and use it to determine whether the asm forces stack alignment or not. gcc consistently does not do this for GCC-style asms; Apple gcc inconsistently sometimes does it for asm blocks. There is no convenient place to put a bit in either the SDNode or the MachineInstr form, so I've added an extra operand to each; unlovely, but it does allow for expansion for more bits, should we need it. PR 5125. Some existing testcases are affected. The operand lists of the SDNode and MachineInstr forms are indexed with awesome mnemonics, like "2"; I may fix this someday, but not now. I'm not making it any worse. If anyone is inspired I think you can find all the right places from this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107506 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a VT argument to getMinimalPhysRegClass and replace the copy related usesRafael Espindola2010-06-29
| | | | | | | | | of getPhysicalRegisterRegClass with it. If we want to make a copy (or estimate its cost), it is better to use the smallest class as more efficient operations might be possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach regular and fast isel to set dead flags on unused implicit defsDan Gohman2010-06-18
| | | | | | | on calls and similar instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106353 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark physregs defined by inline asm as implicit.Jakob Stoklund Olesen2010-06-09
| | | | | | | This is a bit of a hack to make inline asm look more like call instructions. It would be better to produce correct dead flags during isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105749 91177308-0d34-0410-b5e6-96231b3b80d8
* Add argument name comments.Jakob Stoklund Olesen2010-06-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105665 91177308-0d34-0410-b5e6-96231b3b80d8
* Continuously refine the register class of REG_SEQUENCE def with all the ↵Evan Cheng2010-05-18
| | | | | | source registers and sub-register indices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104051 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR7162: Use source register classes and sub-indices to determine the ↵Evan Cheng2010-05-18
| | | | | | correct register class of the definitions of REG_SEQUENCE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104050 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't set kill flags for instructions which the scheduler has cloned.Dan Gohman2010-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103827 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't set kill flags on uses of CopyFromReg nodes. InstrEmitter doesn'tDan Gohman2010-05-11
| | | | | | | | create separate virtual registers for CopyFromReg values, so uses of them don't necessarily kill the value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103519 91177308-0d34-0410-b5e6-96231b3b80d8
* Indentation.Evan Cheng2010-05-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103441 91177308-0d34-0410-b5e6-96231b3b80d8
* SDDbgValues are apparently not being legalized. Fix a symptom of the problem,Dan Gohman2010-05-07
| | | | | | | | and not the real problem itself, by dropping debug info for i128 values. rdar://7958162. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103310 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-06
| | | | | | | doesn't have to guess. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach scheduler about REG_SEQUENCE.Evan Cheng2010-05-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102984 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-enable isel kill flags, now that the local allocator is ignoring them.Dan Gohman2010-05-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102981 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-disable kill flags, as there is more trouble.Dan Gohman2010-05-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102826 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-enable kill flags from SelectionDAGISel, with a fix: don'tDan Gohman2010-05-01
| | | | | | | try to put a kill flag on a DBG_INFO instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102820 91177308-0d34-0410-b5e6-96231b3b80d8
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-01
| | | | | | | changes before doing phi lowering for switches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
* EmitDbgValue doesn't need its EdgeMapping argument.Dan Gohman2010-04-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102742 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily disable SelectionDAG kill flags, which are causing trouble.Dan Gohman2010-04-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102680 91177308-0d34-0410-b5e6-96231b3b80d8
* Set register kill flags on the SelectionDAG path, at least in theDan Gohman2010-04-30
| | | | | | | easy cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102678 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid adding a null MD node operand, which crashes with "-debug" when tryingBob Wilson2010-04-26
| | | | | | | to print the operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102395 91177308-0d34-0410-b5e6-96231b3b80d8
* - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo ↵Evan Cheng2010-04-26
| | | | | | | | | and rename it to emitFrameIndexDebugValue. - Teach spiller to modify DBG_VALUE instructions to reference spill slots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop abusing EmitInstrWithCustomInserter for target-dependentDale Johannesen2010-04-25
| | | | | | | | | | form of DEBUG_VALUE, as it doesn't have reasonable default behavior for unsupported targets. Add a new hook instead. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102320 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete a redundant return statement.Dan Gohman2010-04-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101860 91177308-0d34-0410-b5e6-96231b3b80d8
* Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman2010-04-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
* Have the inst emitter add the !srcloc mdnode to the machine instr.Chris Lattner2010-04-07
| | | | | | | | Have the asmprinter use the mdnode to scavenge a source location if present. Document this nonsense in langref. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100607 91177308-0d34-0410-b5e6-96231b3b80d8
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