| Commit message (Expand) | Author | Age |
|---|
| * | Revert "Give internal classes hidden visibility." | Benjamin Kramer | 2013-09-11 |
| * | Give internal classes hidden visibility. | Benjamin Kramer | 2013-09-11 |
| * | Fix #includes, so we include only what we really need. | Jakub Staszak | 2013-02-20 |
| * | Change TargetLowering::getRepRegClassFor to take an MVT, instead of | Patrik Hagglund | 2012-12-13 |
| * | Revert EVT->MVT changes, r169836-169851, due to buildbot failures. | Patrik Hagglund | 2012-12-11 |
| * | Change TargetLowering::getRepRegClassFor to take an MVT, instead of | Patrik Hagglund | 2012-12-11 |
| * | Add a really faster pre-RA scheduler (-pre-RA-sched=linearize). It doesn't use | Evan Cheng | 2012-10-17 |
| * | misched: remove forceUnitLatencies. Defaults are handled by the default Sched... | Andrew Trick | 2012-10-08 |
| * | Add SelectionDAG::getTargetIndex. | Jakob Stoklund Olesen | 2012-08-07 |
| * | misched: API for minimum vs. expected latency. | Andrew Trick | 2012-06-05 |
| * | misched preparation: rename core scheduler methods for consistency. | Andrew Trick | 2012-03-07 |
| * | misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles. | Andrew Trick | 2012-03-07 |
| * | misched preparation: modularize schedule emission. | Andrew Trick | 2012-03-07 |
| * | misched preparation: modularize schedule printing. | Andrew Trick | 2012-03-07 |
| * | misched preparation: modularize schedule verification. | Andrew Trick | 2012-03-07 |
| * | Cleanup in preparation for misched: Move DAG visualization logic. | Andrew Trick | 2012-03-07 |
| * | Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ... | Andrew Trick | 2012-03-07 |
| * | Add a RegisterMaskSDNode class. | Jakob Stoklund Olesen | 2012-01-18 |
| * | The index stored in the RegDefIter is one after the current index. When gett... | Owen Anderson | 2011-06-27 |
| * | Add a new MVT::untyped. This will be used in future work for modelling ISA f... | Owen Anderson | 2011-06-15 |
| * | Added a check in the preRA scheduler for potential interference on a | Andrew Trick | 2011-04-07 |
| * | Introducing a new method of tracking register pressure. We can't | Andrew Trick | 2011-02-04 |
| * | rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for | Chris Lattner | 2010-12-21 |
| * | Teach if-converter to be more careful with predicating instructions that would | Evan Cheng | 2010-09-10 |
| * | Code refactoring, no functionality changes. | Evan Cheng | 2010-06-10 |
| * | Allow targets more controls on what nodes are scheduled by reg pressure, what... | Evan Cheng | 2010-05-20 |
| * | Add a hybrid bottom up scheduler that reduce register usage while avoiding | Evan Cheng | 2010-05-20 |
| * | Get rid of the EdgeMapping map. Instead, just check for BasicBlock | Dan Gohman | 2010-05-01 |
| * | Three changes: | Chris Lattner | 2010-04-07 |
| * | Teach pre-regalloc scheduler to schedule loads from nearby addresses. It may ... | Evan Cheng | 2010-01-22 |
| * | Initial target-independent CodeGen support for BlockAddresses. | Dan Gohman | 2009-10-30 |
| * | Create a new InstrEmitter class for translating SelectionDAG nodes | Dan Gohman | 2009-10-10 |
| * | The ScheduleDAG framework now requires an AliasAnalysis argument, though | Dan Gohman | 2009-10-09 |
| * | Improve MachineMemOperand handling. | Dan Gohman | 2009-09-25 |
| * | Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ... | Evan Cheng | 2009-09-18 |
| * | Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize | Dan Gohman | 2009-04-13 |
| * | Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS. | Dan Gohman | 2009-04-13 |
| * | When scheduling a block in parts, keep track of the overall | Dan Gohman | 2009-02-11 |
| * | Delete an unused member function. | Dan Gohman | 2009-02-06 |
| * | Move ScheduleDAGSDNodes.h to be a private header. Front-ends | Dan Gohman | 2009-02-06 |
