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path: root/lib/CodeGen/TwoAddressInstructionPass.cpp
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* Reduce indentation with early exit.Jakob Stoklund Olesen2012-10-26
| | | | | | No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166829 91177308-0d34-0410-b5e6-96231b3b80d8
* Also make the current basic block a class member.Jakob Stoklund Olesen2012-10-26
| | | | | | Don't pass it around everywhere as a function argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166828 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the Processed set a class member.Jakob Stoklund Olesen2012-10-26
| | | | | | Don't pass it everywhere as an argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166820 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix whitespace and function names to be coding standardy.Jakob Stoklund Olesen2012-10-26
| | | | | | No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166814 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the canCombineSubRegIndices() target hook.Jakob Stoklund Olesen2012-10-26
| | | | | | | The new coalescer can already do all of this, so there is no need to duplicate the efforts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166813 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop adding <imp-def> operands when expanding REG_SEQUENCE.Jakob Stoklund Olesen2012-09-17
| | | | | | | | | | These extra operands are not needed by register allocators using VirtRegRewriter, and RAFast don't need them any longer. By omitting the <imp-def> operands, it becomes possible for the new register coalescer to track which lanes are valid and which are undef. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164073 91177308-0d34-0410-b5e6-96231b3b80d8
* Search the whole instruction for tied operands.Jakob Stoklund Olesen2012-09-04
| | | | | | | Implicit uses can be dynamically tied to defs. This will soon be used for predicated instructions on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163177 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-22
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162347 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the TII::scheduleTwoAddrSource() hook.Jakob Stoklund Olesen2012-08-13
| | | | | | | | | | | | | | | It never does anything when running 'make check', and it get's in the way of updating live intervals in 2-addr. The hook was originally added to help form IT blocks in Thumb2 code before register allocation, but the pass ordering has changed since then, and we run if-conversion after register allocation now. When the MI scheduler is enabled, there will be no less than two schedulers between 2-addr and Thumb2ITBlockPass, so this hook is unlikely to help anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161794 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a future TwoAddressInstructionPass crash.Jakob Stoklund Olesen2012-08-09
| | | | | | | No test case, the crash only happens when the default use list order is changed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161627 91177308-0d34-0410-b5e6-96231b3b80d8
* Skip tied operand pairs that already have the same register.Jakob Stoklund Olesen2012-08-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161454 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete a dead variable.Jakob Stoklund Olesen2012-08-04
| | | | | | TwoAddressInstructionPass doesn't remat any more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161285 91177308-0d34-0410-b5e6-96231b3b80d8
* TwoAddressInstructionPass refactoring: Extract another method.Jakob Stoklund Olesen2012-08-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161284 91177308-0d34-0410-b5e6-96231b3b80d8
* TwoAddressInstructionPass refactoring: Extract a method.Jakob Stoklund Olesen2012-08-03
| | | | | | | No functional change intended, except replacing a DenseMap with a SmallDenseMap which should behave identically. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161281 91177308-0d34-0410-b5e6-96231b3b80d8
* Begin adding support for updating LiveIntervals in TwoAddressInstructionPass.Jakob Stoklund Olesen2012-08-03
| | | | | | | This is far from complete, and only changes behavior when the -early-live-intervals flag is passed to llc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161273 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete dead function.Jakob Stoklund Olesen2012-08-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161242 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't delete dead code in TwoAddressInstructionPass.Jakob Stoklund Olesen2012-08-03
| | | | | | | This functionality was added before we started running DeadMachineInstructionElim on all targets. It serves no purpose now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161241 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable rematerialization in TwoAddressInstructionPass.Manman Ren2012-07-25
| | | | | | | | | | | | It is redundant; RegisterCoalescer will do the remat if it can't eliminate the copy. Collected instruction counts before and after this. A few extra instructions are generated due to spilling but it is normal to see these kinds of changes with almost any small codegen change, according to Jakob. This also fixed rdar://11830760 where xor is expected instead of movi0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160749 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a somewhat nasty crasher in PR13378. This crashes inside ofChandler Carruth2012-07-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LiveIntervals due to the two-addr pass generating bogus MI code. The crux of the issue was a loop nesting problem. The intent of the code which attempts to transform instructions before converting them to two-addr form is to defer and reprocess any transformed instructions as the second processing is likely to have more opportunities to coalesce copies, etc. Unfortunately, there was one section of processing that was not deferred -- the INSERT_SUBREG rewriting. Due to quirks of how this rewriting proceeded, not only did it occur early, it removed the bits of information needed for the deferred processing to correctly generate the necessary two address form (specifically inserting a copy), but didn't trigger any immediate assertions and produced what appeared to be already valid two-address from code. Thus, the assertion only fired much later in the pipeline. The fix is to hoist the transformation logic up layer to where it can more firmly defer all further processing, and to teach the normal processing to handle an edge case previously handled as part of the transformation logic. This edge case (already matched tied register operands) needs to *not* defer any steps. As has been brought up repeatedly in the process: wow does this code need refactoring. I *may* squeeze in some time to at least bring sanity to this loop... but wow... =] Thanks to Jakob for helpful hints on the way here, and the review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160443 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some trace output to TwoAddressInstructionPass.Jakob Stoklund Olesen2012-07-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160380 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r160194, switching to use LV information for finding local kills.Chandler Carruth2012-07-15
| | | | | | | | | | | | | | | | | | | | | The notable fix is to look at any dependencies attached to the kill instruction (or other instructions between MI nad the kill) where the dependencies are specific to the register in question. The old code implicitly handled this by rejecting the transform if *any* other uses were found within the block, but after the start point. The new code directly finds the kill, and has to re-use the existing dependency scan to check for non-kill uses. This was caught by self-host, but I found the bug via inspection and use of absurd assert scaffolding to compute the kills in two ways and compare them. So I have no useful testcase for this other than "bootstrap". I'd work harder to reduce a test case if this particular code were likely to live for a long time. Thanks to Benjamin Kramer for reviewing the fix itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160228 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r160194, which switched to use LV information for finding localChandler Carruth2012-07-13
| | | | | | | | kills. This is causing miscompiles that I'm working on tracking down. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160196 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the LiveVariables information to efficiently get local kills. ThisChandler Carruth2012-07-13
| | | | | | | | | | removes the largest scaling problem in the test cases from PR13225 when ASan is switched to insert basic blocks in the natural CFG order. It may also solve some scaling problems for more normal code with large numbers of basic blocks and variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160194 91177308-0d34-0410-b5e6-96231b3b80d8
* Added assertion in getVRegDef of MachineRegisterInfo to make sure the virtualManman Ren2012-07-02
| | | | | | | | register does not have multiple definitions. Modified TwoAddressInstructionPass to use getUniqueVRegDef instead of getVRegDef. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159545 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle <undef> operands in TwoAddressInstructionPass.Jakob Stoklund Olesen2012-06-25
| | | | | | | | | | | | | | | | | When the source register to a 2-addr instruction is undefined, there is no need to attempt any transformations - simply replace the source register with the destination register. This also comes up when lowering IMPLICIT_DEF instructions - make sure the <undef> flag is moved to the new partial register def operand: %vreg8<def> = INSERT_SUBREG %vreg9<undef>, %vreg0<kill>, sub_16bit rewrite undef: %vreg8<def> = INSERT_SUBREG %vreg8<undef>, %vreg0<kill>, sub_16bit convert to: %vreg8:sub_16bit<def,read-undef> = COPY %vreg0<kill> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159120 91177308-0d34-0410-b5e6-96231b3b80d8
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-05
| | | | | | | Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly constrain register classes in 2-addr.Jakob Stoklund Olesen2012-05-20
| | | | | | | X86 has 2-addr instructions with different constraints on the tied def and use operands. One is GR32, one is GR32_NOSP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157149 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach two-address pass to update the "source" map so it doesn't perform aEvan Cheng2012-05-18
| | | | | | | | | | non-profitable commute using outdated info. The test case would still fail because of poor pre-RA schedule. That will be fixed by MI scheduler. rdar://11472010 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157038 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-07
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix two-address pass's aggressive instruction commuting heuristics. It's meantEvan Cheng2012-05-03
| | | | | | | | | | | | | | | | | | | | | | | to catch cases like: %reg1024<def> = MOV r1 %reg1025<def> = MOV r0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 By commuting ADD, it let coalescer eliminate all of the copies. However, there was a bug in the heuristics where it ended up commuting the ADD in: %reg1024<def> = MOV r0 %reg1025<def> = MOV 0 %reg1026<def> = ADD %reg1024, %reg1025 r0 = MOV %reg1026 That did no benefit but rather ensure the last MOV would not be coalesced. rdar://11355268 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156048 91177308-0d34-0410-b5e6-96231b3b80d8
* Added TargetRegisterInfo::getAllocatableClass.Andrew Trick2012-05-03
| | | | | | | | | | The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156046 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch r153892 for PR11861 apparently broke an external project (see PR12493).Lang Hames2012-04-09
| | | | | | | | | | | | This patch restores TwoAddressInstructionPass's pre-r153892 behaviour when rescheduling instructions in TryInstructionTransform. Hopefully this will fix PR12493. To refix PR11861, lowering of INSERT_SUBREGS is deferred until after the copy that unties the operands is emitted (this seems to be a more appropriate fix for that issue anyway). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154338 91177308-0d34-0410-b5e6-96231b3b80d8
* REG_SEQUENCE expansion to COPY instructions wasn't taking account of sub ↵Pete Cooper2012-04-04
| | | | | | register indices on the source registers. No simple test case git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154051 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove spurious debug output.Jakob Stoklund Olesen2012-04-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154032 91177308-0d34-0410-b5e6-96231b3b80d8
* During two-address lowering, rescheduling an instruction does not untieLang Hames2012-04-02
| | | | | | | | operands. Make TryInstructionTransform return false to reflect this. Fixes PR11861. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153892 91177308-0d34-0410-b5e6-96231b3b80d8
* RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick2012-02-10
| | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2012-02-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149671 91177308-0d34-0410-b5e6-96231b3b80d8
* Set correct <def,undef> flags when lowering REG_SEQUENCE.Jakob Stoklund Olesen2012-01-24
| | | | | | | | | | | | | | | | | | | | A REG_SEQUENCE instruction is lowered into a sequence of partial defs: %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0 %vreg7:ssub_1<def> = COPY %vreg2 %vreg7:ssub_2<def> = COPY %vreg2 %vreg7:ssub_3<def> = COPY %vreg2 The first def needs an <undef> flag to indicate it is the beginning of the live range, while the other defs are read-modify-write. Previously, we depended on LiveIntervalAnalysis to notice and fix the missing <def,undef>, but that solution was never robust, it was causing problems with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE instructions. This fixes PR11841. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148879 91177308-0d34-0410-b5e6-96231b3b80d8
* Preserve <def,undef> flags in CoalesceExtSubRegs.Jakob Stoklund Olesen2012-01-24
| | | | | | | This won't have an effect until EliminateRegSequences() starts setting the undef flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148779 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ISD::REG_SEQUENCE to accept physical registers and change ↵Pete Cooper2012-01-18
| | | | | | TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148377 91177308-0d34-0410-b5e6-96231b3b80d8
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-07
| | | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify code. No functionality change.Benjamin Kramer2011-12-03
| | | | | | -3% on ARMDissasembler.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145773 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable expensive two-address optimizations at -O0. rdar://10453055Evan Cheng2011-11-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144806 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable the assertion again. Looks like fastisel is still generating bad ↵Evan Cheng2011-11-16
| | | | | | kill markers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144804 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r144568 now that r144730 has fixed the fast-isel kill marker bug.Evan Cheng2011-11-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144776 91177308-0d34-0410-b5e6-96231b3b80d8
* If the 2addr instruction has other kills, don't move it below any other uses ↵Evan Cheng2011-11-16
| | | | | | since we don't want to extend other live ranges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144772 91177308-0d34-0410-b5e6-96231b3b80d8
* RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE ↵Evan Cheng2011-11-16
| | | | | | instructions. rdar://10451185 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144771 91177308-0d34-0410-b5e6-96231b3b80d8
* Process all uses first before defs to accurately capture register liveness. ↵Evan Cheng2011-11-16
| | | | | | rdar://10449480 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144770 91177308-0d34-0410-b5e6-96231b3b80d8
* Set SeenStore to true to prevent loads from being moved; also eliminates a ↵Evan Cheng2011-11-15
| | | | | | non-deterministic behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144628 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid dereferencing off the beginning of lists.Evan Cheng2011-11-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144569 91177308-0d34-0410-b5e6-96231b3b80d8
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