| Commit message (Expand) | Author | Age |
|---|
| ... | |
| * | Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE ba... | Lang Hames | 2012-02-17 |
| * | Oop - r150653 + r150654 broke one of my test cases. Backing out for now... | Lang Hames | 2012-02-16 |
| * | FPSCR shouldn't be reserved. | Lang Hames | 2012-02-16 |
| * | More dead code removal (using -Wunreachable-code) | David Blaikie | 2012-01-20 |
| * | Implement ARMBaseRegisterInfo::getCallPreservedMask(). | Jakob Stoklund Olesen | 2012-01-17 |
| * | Reapply r146997, "Heed spill slot alignment on ARM." | Jakob Stoklund Olesen | 2012-01-05 |
| * | Avoid reserving an ARM base pointer during register allocation. | Jakob Stoklund Olesen | 2012-01-05 |
| * | Revert r146997, "Heed spill slot alignment on ARM." | Jakob Stoklund Olesen | 2012-01-03 |
| * | Heed spill slot alignment on ARM. | Jakob Stoklund Olesen | 2011-12-20 |
| * | ARM target code clean up. Check for iOS, not Darwin where it makes sense. | Evan Cheng | 2011-12-20 |
| * | Emit a getMatchingSuperRegClass() implementation for every target. | Jakob Stoklund Olesen | 2011-12-19 |
| * | Move global variables in TargetMachine into new TargetOptions class. As an API | Nick Lewycky | 2011-12-02 |
| * | Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :( | Chad Rosier | 2011-10-20 |
| * | Add support for dynamic stack realignment when in thumb1 mode. | Chad Rosier | 2011-10-18 |
| * | Revert r141529. This is causing failures in the test-suite, like bigstack and... | Bill Wendling | 2011-10-11 |
| * | When getting the number of bits necessary for addressing mode | Bill Wendling | 2011-10-10 |
| * | Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions." | Chad Rosier | 2011-10-01 |
| * | Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact | Chad Rosier | 2011-10-01 |
| * | Store sub-class lists as a bit vector. | Jakob Stoklund Olesen | 2011-09-30 |
| * | Tidy up a bit. | Jim Grosbach | 2011-09-13 |
| * | Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical | Evan Cheng | 2011-08-30 |
| * | Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. | Jim Grosbach | 2011-08-24 |
| * | Silence a bunch (but not all) "variable written but not read" warnings | Duncan Sands | 2011-08-12 |
| * | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng | 2011-07-20 |
| * | Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for | Evan Cheng | 2011-07-18 |
| * | Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down | Evan Cheng | 2011-07-18 |
| * | Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previ... | Frits van Bommel | 2011-07-18 |
| * | Next round of MC refactoring. This patch factor MC table instantiations, MC | Evan Cheng | 2011-07-14 |
| * | Remove redundant Thumb2 ADD/SUB SP instruction definitions. | Jim Grosbach | 2011-06-29 |
| * | Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. | Evan Cheng | 2011-06-28 |
| * | Hide more details in tablegen generated MCRegisterInfo ctor function. | Evan Cheng | 2011-06-28 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 |
| * | More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo. | Evan Cheng | 2011-06-27 |
| * | Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc | Evan Cheng | 2011-06-27 |
| * | Starting to refactor Target to separate out code that's needed to fully describe | Evan Cheng | 2011-06-24 |
| * | Reserve D16-D13 on subtargets that don't support them. | Jakob Stoklund Olesen | 2011-06-18 |
| * | Explicitly invoke ArrayRef constructor to keep gcc happy. | Jakob Stoklund Olesen | 2011-06-17 |
| * | Rename TRI::getAllocationOrder() to getRawAllocationOrder(). | Jakob Stoklund Olesen | 2011-06-16 |
| * | Use the dwarf->llvm mapping to print register names in the cfi | Rafael Espindola | 2011-05-30 |
| * | Reuse the TargetInstrDesc. | Cameron Zwarich | 2011-05-19 |
| * | Correctly constrain a register class when computing frame offsets, as the Thumb2 | Cameron Zwarich | 2011-05-19 |
| * | Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on regist... | Jakob Stoklund Olesen | 2011-04-26 |
| * | Avoid write-after-write issue hazards for Cortex-A9. | Bob Wilson | 2011-04-19 |
| * | Fix a ton of comment typos found by codespell. Patch by | Chris Lattner | 2011-04-15 |
| * | Ignore special ARM allocation hints for unexpected register classes. | Jakob Stoklund Olesen | 2011-03-25 |
| * | Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo. | Cameron Zwarich | 2011-03-07 |
| * | Implement frame unwinding information emission for Thumb1. Not finished yet b... | Anton Korobeynikov | 2011-03-05 |
| * | Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs a... | Anton Korobeynikov | 2011-01-10 |
| * | Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. | Jakob Stoklund Olesen | 2011-01-10 |
| * | During local stack slot allocation, the materializeFrameBaseRegister function | Bill Wendling | 2010-12-17 |
