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path: root/lib/Target/ARM/ARMCodeEmitter.cpp
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* Revert r121721, which broke buildbots.Owen Anderson2010-12-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121726 91177308-0d34-0410-b5e6-96231b3b80d8
* Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. ↵Owen Anderson2010-12-13
| | | | | | | | | Provide correct fixups for Thumb2 ADR, which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121721 91177308-0d34-0410-b5e6-96231b3b80d8
* In Thumb2, direct branches can be encoded as either a "short" conditional ↵Owen Anderson2010-12-13
| | | | | | | | | | | branch with a null predicate, or as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise equivalence, provide encoding and fixup support for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121710 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding of Thumb1 LDRB and STRB.Owen Anderson2010-12-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121581 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb unconditional branch binary encoding. rdar://8754994Jim Grosbach2010-12-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121496 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb conditional branch binary encodings. rdar://8745367Jim Grosbach2010-12-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121493 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of theBill Wendling2010-12-09
| | | | | | | | t_addrmode_s# address modes is used for ASM printing, not for encoding. <rdar://problem/8745375> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121417 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the encoder method for t_cbtarget to match.Jim Grosbach2010-12-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121399 91177308-0d34-0410-b5e6-96231b3b80d8
* The BLX instruction is encoded differently than the BL, because why not? InBill Wendling2010-12-09
| | | | | | | | | | | particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0' always. Going through the BL fixup encoding was trashing the "bit 0 is '0'" invariant. Attempt to get the encoding at slightly more correct with this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121336 91177308-0d34-0410-b5e6-96231b3b80d8
* Support the "target" encodings for the CB[N]Z instructions.Bill Wendling2010-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121308 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for loading from a constant pool.Bill Wendling2010-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121226 91177308-0d34-0410-b5e6-96231b3b80d8
* Binary encoding for ARM tLDRspi and tSTRspi.Jim Grosbach2010-12-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121186 91177308-0d34-0410-b5e6-96231b3b80d8
* Add fixup for Thumb1 BL/BLX instructions.Jim Grosbach2010-12-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121072 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a post encoder method to the VFP instructions to convert them to the Thumb2Bill Wendling2010-12-01
| | | | | | | encoding if we're in that mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120608 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADRJim Grosbach2010-12-01
| | | | | | | instruction at MC lowering. Add binary encoding information for the ADR, including fixup data for the label operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120594 91177308-0d34-0410-b5e6-96231b3b80d8
* Add correct encodings for STRD and LDRD, including fixup support. ↵Owen Anderson2010-12-01
| | | | | | Additionally, update these to unified syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120589 91177308-0d34-0410-b5e6-96231b3b80d8
* * Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same asBill Wendling2010-11-30
| | | | | | | | | | | t_addrmode_s4, but with a different scaling factor. * Encode the Thumb1 load and store instructions. This involved a bit of refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and were removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120482 91177308-0d34-0410-b5e6-96231b3b80d8
* Add encoding support for Thumb2 PLD and PLI instructions.Owen Anderson2010-11-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120449 91177308-0d34-0410-b5e6-96231b3b80d8
* Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almostBill Wendling2010-11-30
| | | | | | | | | | | certainly be made more generic. But it does allow us to parse something like: ldr r3, [r2, r4] correctly in Thumb mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120408 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename BX/BRIND/etc patterns to clarify which is actually the BX instructionJim Grosbach2010-11-30
| | | | | | and which are pseudos. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120366 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct Thumb2 encodings for a much wider range of loads and stores.Owen Anderson2010-11-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120364 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the encoding of VLD4-dup alignment.Bob Wilson2010-11-30
| | | | | | | | The only reasonable way I could find to do this is to provide an alternate version of the addrmode6 operand with a different encoding function. Use it for all the VLD-dup instructions for the sake of consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120358 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide Thumb2 encodings for basic loads and stores.Owen Anderson2010-11-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120340 91177308-0d34-0410-b5e6-96231b3b80d8
* Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the sameBill Wendling2010-11-20
| | | | | | | value that the one in ARMMCCodeEmitter.cpp does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119878 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor cleanups to a few llvm_unreachable() calls.Jim Grosbach2010-11-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119767 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the ↵Jason W Kim2010-11-18
| | | | | | | | | | | .o path now works for ARM. Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired. Existing tests cover this update. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119760 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up LEApcrel instuction(s) a bit. It's not really a Pseudo, so don't markJim Grosbach2010-11-17
| | | | | | it as such. Add some encoding information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119588 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment typo.Jim Grosbach2010-11-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119573 91177308-0d34-0410-b5e6-96231b3b80d8
* The machine instruction no longer encodes the submode as a separate operand. WeBill Wendling2010-11-17
| | | | | | | should get the submode from the load/store multiple instruction's opcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119461 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.Jim Grosbach2010-11-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119180 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either ↵Evan Cheng2010-11-12
| | | | | | movi+orr or movw+movt depending on the subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118938 91177308-0d34-0410-b5e6-96231b3b80d8
* First stab at providing correct Thumb2 encodings, start with adc.Owen Anderson2010-11-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118924 91177308-0d34-0410-b5e6-96231b3b80d8
* Fill out support for Thumb2 encodings of NEON instructions.Owen Anderson2010-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118854 91177308-0d34-0410-b5e6-96231b3b80d8
* Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].Owen Anderson2010-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118843 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for Thumb2 encodings of NEON data processing instructions, using ↵Owen Anderson2010-11-11
| | | | | | | | | the new PostEncoderMethod infrastructure. More tests to come. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
* Encoding of destination fixup for ARM branch and conditional branchJim Grosbach2010-11-11
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118801 91177308-0d34-0410-b5e6-96231b3b80d8
* Encoding for ARM LDRSH_POST.Jim Grosbach2010-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118794 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM STRH encoding information.Jim Grosbach2010-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118757 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM LDM encoding for the mode (ia, ib, da, db) operand.Jim Grosbach2010-11-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118736 91177308-0d34-0410-b5e6-96231b3b80d8
* Add encoder method for ARM load/store shifted register offset operands.Jim Grosbach2010-11-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
* The MC code couldn't handle ARM LDR instructions with negative offsets:Bill Wendling2010-11-03
| | | | | | | | | | | | | vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to workBill Wendling2010-11-02
| | | | | | | | | with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename encoder methods to match naming convention.Owen Anderson2010-11-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118093 91177308-0d34-0410-b5e6-96231b3b80d8
* Add correct NEON encodings for vld2, vld3, and vld4 basic variants.Owen Anderson2010-11-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117997 91177308-0d34-0410-b5e6-96231b3b80d8
* Add correct NEON encodings for the "multiple single elements" form of vld.Owen Anderson2010-11-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
* Encode the register list operands for ARM mode LDM/STM instructions.Jim Grosbach2010-10-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117753 91177308-0d34-0410-b5e6-96231b3b80d8
* 80 column fix.Jim Grosbach2010-10-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117741 91177308-0d34-0410-b5e6-96231b3b80d8
* s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operandJim Grosbach2010-10-29
| | | | | | encoder functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117738 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-27
| | | | | | | | the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide correct encodings for NEON vcvt, which has its own special immediate ↵Owen Anderson2010-10-27
| | | | | | | | | encoding for specifying fractional bits for fixed point conversions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
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