| Commit message (Expand) | Author | Age |
|---|
| * | ARM: produce friendly error for invalid inline asm | Tim Northover | 2013-11-14 |
| * | Enable optimization of sin / cos pair into call to __sincos_stret for iOS7+. | Bob Wilson | 2013-11-03 |
| * | Legalize: Improve legalization of long vector extends. | Jim Grosbach | 2013-10-31 |
| * | Struct byval cleanup: add helper functions to reduce code duplication. | Manman Ren | 2013-10-29 |
| * | ARM: don't expand atomicrmw inline on Cortex-M0 | Tim Northover | 2013-10-25 |
| * | ARM: Tweak usage of '*vfp' compiler_rt functions. | Jim Grosbach | 2013-10-24 |
| * | Remove class abstraction from ARM struct byval lowering | David Peixotto | 2013-10-24 |
| * | ARM: Use non-VFP softcalls on embedded Darwinish targets | Tim Northover | 2013-10-24 |
| * | 17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets | David Peixotto | 2013-10-17 |
| * | Refactor lowering for COPY_STRUCT_BYVAL_I32 | David Peixotto | 2013-10-17 |
| * | Struct byval: fix a copy-paste error for thumb2. | Manman Ren | 2013-10-15 |
| * | Struct byval: use the correct alignment for loads generated to load | Manman Ren | 2013-10-07 |
| * | ARM: do not add a regmask for TAILJUMPs | Matthias Braun | 2013-10-04 |
| * | ARM: support interrupt attribute | Tim Northover | 2013-10-01 |
| * | [ARM] Use the load-acquire/store-release instructions optimally in AArch32. | Amara Emerson | 2013-09-26 |
| * | Fix PR 17368: disable vector mul distribution for square of add/sub for ARM | Weiming Zhao | 2013-09-25 |
| * | [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line options | Joey Gouly | 2013-09-13 |
| * | [ARMv8] Implement the new DMB/DSB operands. | Joey Gouly | 2013-09-05 |
| * | Clean up some usage of Triple. The base class has methods for determining if... | Cameron Esfahani | 2013-08-29 |
| * | ARM: Use "dmb sy" for barriers on M-class CPUs | Tim Northover | 2013-08-28 |
| * | [ARMv8] Add CodeGen for VMAXNM/VMINNM. | Joey Gouly | 2013-08-23 |
| * | [ARMv8] Add CodeGen support for VSEL. | Joey Gouly | 2013-08-22 |
| * | [ARM] Constrain some register classes in EmitAtomicBinary64 so that | Joey Gouly | 2013-08-22 |
| * | ARM: implement some simple f64 materializations. | Tim Northover | 2013-08-20 |
| * | ARM: implement allowTruncateForTailCall | Tim Northover | 2013-08-06 |
| * | [ARM] check bitwidth in PerformORCombine | Saleem Abdulrasool | 2013-07-30 |
| * | [ARM][ISel] Improve the lowering of vector loads. | Quentin Colombet | 2013-07-23 |
| * | ARM: allow printing of ARM atomic DAG nodes. | Tim Northover | 2013-07-16 |
| * | ARM: implement ldrex, strex and clrex intrinsics | Tim Northover | 2013-07-16 |
| * | ARM EABI divmod support | Renato Golin | 2013-07-16 |
| * | Use llvm::array_lengthof to replace sizeof(array)/sizeof(array[0]). | Craig Topper | 2013-07-15 |
| * | Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector s... | Craig Topper | 2013-07-14 |
| * | ARM: Improve codegen for generic vselect. | Jim Grosbach | 2013-07-08 |
| * | Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes. | Jakob Stoklund Olesen | 2013-07-04 |
| * | Revert r185595-185596 which broke buildbots. | Jakob Stoklund Olesen | 2013-07-04 |
| * | Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes. | Jakob Stoklund Olesen | 2013-07-03 |
| * | [ARM] Improve the instruction selection of vector loads. | Quentin Colombet | 2013-07-03 |
| * | ARM: relax the atomic release barrier to "dmb ishst" on Swift | Tim Northover | 2013-07-03 |
| * | Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst") | Tim Northover | 2013-07-01 |
| * | ARM: relax the atomic release barrier to "dmb ishst" | Tim Northover | 2013-07-01 |
| * | ARM: ensure fixed-point conversions have sane types | Tim Northover | 2013-06-28 |
| * | ARM: Proactively ensure that the LowerCallResult hack for 'this'-returns is n... | Stephen Lin | 2013-06-26 |
| * | The getRegForInlineAsmConstraint function should only accept MVT value types. | Chad Rosier | 2013-06-22 |
| * | [ARMTargetLowering] ARMISD::{SUB,ADD}{C,E} second result is a boolean implyin... | Michael Gottesman | 2013-06-18 |
| * | Converted an overly aggressive assert to a conditional check in AddCombineTo6... | Michael Gottesman | 2013-06-18 |
| * | Order CALLSEQ_START and CALLSEQ_END nodes. | Andrew Trick | 2013-05-29 |
| * | Track IR ordering of SelectionDAG nodes 2/4. | Andrew Trick | 2013-05-25 |
| * | Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. | Michael J. Spencer | 2013-05-24 |
| * | ARM: implement @llvm.readcyclecounter intrinsic | Tim Northover | 2013-05-23 |
| * | PR15868 fix. | Stepan Dyatkovskiy | 2013-05-20 |
