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path: root/lib/Target/ARM/ARMInstrThumb2.td
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* ARM assembly aliases for BIC<-->AND (immediate).Jim Grosbach2011-12-09
| | | | | | | | | | | | When the immediate operand of an AND or BIC instruction isn't representable in the immediate field of the instruction, but the bitwise negation of the immediate is, assemble the instruction as the inverse operation instead with the inverted immediate as the operand. rdar://10550057 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 alias for long-form pop and friends.Jim Grosbach2011-12-07
| | | | | | rdar://10542474 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2: MUL two-operand form encoding operand order fix.Jim Grosbach2011-12-06
| | | | | | | | | Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we match gas. rdar://10532439 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 two-operand 'mul' instruction wide encoding parsing.Jim Grosbach2011-11-15
| | | | | | rdar://10449724 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144684 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM refactor simple immediate asm operand render methods.Jim Grosbach2011-11-12
| | | | | | | These immediate operands all use the same simple logic for rendering to MCInst, so have them share the method for doing so. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144439 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing STMDB w/ optional .w suffix.Jim Grosbach2011-11-09
| | | | | | | rdar://10422955 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".Jim Grosbach2011-10-28
| | | | | | | | | | | | When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example, mov r2, #-3 becomes mvn r2, #2 rdar://10349224 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143235 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 ADD/SUB instructions encoding selection outside IT block.Jim Grosbach2011-10-28
| | | | | | | | | | | | Outside an IT block, "add r3, #2" should select a 32-bit wide encoding rather than generating an error indicating the 16-bit encoding is only legal in an IT block (outside, the 'S' suffic is required for the 16-bit encoding). rdar://10348481 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143201 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.Jim Grosbach2011-10-27
| | | | | | rdar://10348844 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143110 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.Jim Grosbach2011-10-27
| | | | | | | rdar://10348584 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143108 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 ldr pc-relative encoding fixes.Jim Grosbach2011-10-26
| | | | | | | | | We were parsing label references to the i12 encoding, which isn't right. They need to go to the pci variant instead. More of rdar://10348687 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143068 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.Jim Grosbach2011-10-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143034 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 LDM instructions can target PC. Make sure to encode it.Jim Grosbach2011-10-24
| | | | | | | PR11220 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142801 91177308-0d34-0410-b5e6-96231b3b80d8
* Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.Andrew Trick2011-10-18
| | | | | | | | | Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142397 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2011-10-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142394 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it.Jim Grosbach2011-10-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142363 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix misc warnings. Patch by Joe Abbey.Eli Friedman2011-10-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142332 91177308-0d34-0410-b5e6-96231b3b80d8
* Now Igor, throw the switch...give my creation life!Bill Wendling2011-10-17
| | | | | | | | | | | | | | | | | | Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the SjLj dispatch table in IR, where it frequently violates serveral assumptions -- in particular assumptions made by the landingpad instruction about what can branch to a landing pad and what cannot. Performing this in the back-end allows us to violate these assumptions without the IR getting angry at us. It also allows us to perform a small optimization. We can shove the address of the dispatch's basic block into the function context and not have to add code around the setjmp to check for the return value and jump to the dispatch. Neat, huh? <rdar://problem/10116753> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142294 91177308-0d34-0410-b5e6-96231b3b80d8
* Pseudoinstructions should not be less constrained than the instruction they areCameron Zwarich2011-10-17
| | | | | | lowered to. This fixes a lot of verifier failures on the test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142254 91177308-0d34-0410-b5e6-96231b3b80d8
* Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads.Cameron Zwarich2011-10-16
| | | | | | | These missing flags show up as errors when running -verify-coalescing on test-suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142111 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an obvious typo found when looking at nearby code.Cameron Zwarich2011-10-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142110 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach2011-10-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r141365 now that PR11107 is fixed.Bill Wendling2011-10-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame toBill Wendling2011-10-10
| | | | | | | hang, and possibly SPEC/CINT2006/464_h264ref. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
* Peephole optimization for ABS on ARM.Anton Korobeynikov2011-10-07
| | | | | | | Patch by Ana Pazos! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding back support for printing operands symbolically to ARM's new disassemblerKevin Enderby2011-10-04
| | | | | | | | | | | | | | | | | | | | using llvm's public 'C' disassembler API now including annotations. Hooked this up to Darwin's otool(1) so it can again print things like branch targets for example this: blx _puts instead of this: blx #-36 and includes support for annotations for branches to symbol stubs like: bl 0x40 @ symbol stub for: _puts and annotations for pc relative loads like this: ldr r3, #8 @ literal pool for: Hello, world! Also again can print the expression encoded in the Mach-O relocation entries for things like this: movt r0, :upper16:((_foo-_bar)+1234) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 ADD/SUB can take SP as a destination register.Jim Grosbach2011-10-03
| | | | | | | It's documented as a separate instruction to line up with the Thumb1 encodings, for which it really is a distinct instruction encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141020 91177308-0d34-0410-b5e6-96231b3b80d8
* Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy2011-09-28
| | | | | | | | | | | | | forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.Jim Grosbach2011-09-27
| | | | | | | | | Add inst alias to handle these assembly forms. Add tests, too. rdar://10178799 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140647 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove extraneous commit garbage.Owen Anderson2011-09-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140581 91177308-0d34-0410-b5e6-96231b3b80d8
* ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson2011-09-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more fixed bits to USAT16 encoding to filter out incorrect decodings.Owen Anderson2011-09-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140422 91177308-0d34-0410-b5e6-96231b3b80d8
* Post-index loads/stores in still need to print the post-indexed immediate, ↵Owen Anderson2011-09-23
| | | | | | even if it's zero, to distinguish them from non-post-indexed instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8
* Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix ↵Owen Anderson2011-09-21
| | | | | | other test failures I caused. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140284 91177308-0d34-0410-b5e6-96231b3b80d8
* Print out immediate offset versions of PC-relative load/store instructions ↵Owen Anderson2011-09-21
| | | | | | as [pc, #123] rather than simply #123. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140283 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick2011-09-21
| | | | | | | | | | | | | | This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
* Restore hasPostISelHook tblgen flag.Andrew Trick2011-09-20
| | | | | | | | | | | No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM isel bug fix for adds/subs operands.Andrew Trick2011-09-20
| | | | | | | | | | | | Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.Jim Grosbach2011-09-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140125 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove incorrect comments. These are not disassmebly only patterns.Jim Grosbach2011-09-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140116 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 range check on CPS mode immediate.Jim Grosbach2011-09-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140105 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up comments.Jim Grosbach2011-09-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140099 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for TBB/TBH.Jim Grosbach2011-09-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up a bit.Jim Grosbach2011-09-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140050 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.Jim Grosbach2011-09-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8
* Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the ↵Owen Anderson2011-09-19
| | | | | | decoder from emitting gibberish for this invalid encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140041 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH.Jim Grosbach2011-09-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140029 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for SUB(immediate).Jim Grosbach2011-09-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139966 91177308-0d34-0410-b5e6-96231b3b80d8
* Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.Owen Anderson2011-09-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139958 91177308-0d34-0410-b5e6-96231b3b80d8
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