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* Add LLVM support for Swift.Bob Wilson2012-09-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
* fp16-to-fp32 conversion instructions are available in Thumb mode as well.Anton Korobeynikov2012-08-18
| | | | | | | Make sure the generic pattern is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162170 91177308-0d34-0410-b5e6-96231b3b80d8
* Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows ↵Evan Cheng2012-08-15
| | | | | | unaligned access. rdar://12091029 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161962 91177308-0d34-0410-b5e6-96231b3b80d8
* The names of VFP variants of half-to-float conversion instructions wereAnton Korobeynikov2012-08-14
| | | | | | | | | reversed. This leads to wrong codegen for float-to-half conversion intrinsics which are used to support storage-only fp16 type. NEON variants of same instructions are fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161907 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-10
| | | | | | single-precision resiters) (and do it properly this time! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r159938 (and r159945) to appease the buildbots.Chad Rosier2012-07-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-09
| | | | | | single-precision resiters) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a missing llvm.fma -> VFNMS pattern to the ARM backend.Lang Hames2012-06-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158902 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the order of the operands in the llvm.fma intrinsic patterns for ARM,Lang Hames2012-04-27
| | | | | | | | <rdar://problem/11325085>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155724 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. 80 columns, whitespace, et. al.Jim Grosbach2012-04-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155399 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM some VFP tblgen'erated two-operand aliases.Jim Grosbach2012-04-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155178 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more fused mul+add/sub patterns. rdar://10139676Evan Cheng2012-04-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154484 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up ARM fused multiply + add/sub support some more: rename some iselEvan Cheng2012-04-11
| | | | | | | | | | | | predicates. Also remove NEON2 since it's not really useful and it is confusing. If NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it really mean? rdar://10139676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154480 91177308-0d34-0410-b5e6-96231b3b80d8
* Match (fneg (fma) to vfnma. rdar://10139676Evan Cheng2012-04-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154469 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle llvm.fma.* intrinsics. rdar://10914096Evan Cheng2012-04-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154439 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM divided syntax fmrx/fmxr mnemonics.Jim Grosbach2012-03-16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152946 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM vmrs system registers mvfr0 and mvfr1 handling.Jim Grosbach2012-03-16
| | | | | | rdar://11058464 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152881 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM case-insensitive checking for APSR_nzcv.Jim Grosbach2012-03-15
| | | | | | rdar://11056591 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM aliases for pre-unified syntax fcmpz[sd] mnemonics.Jim Grosbach2012-03-15
| | | | | | rdar://11056647 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152834 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix VCVT decoding (between floating-point and fixed-point, Floating-point). ↵Kristof Beyls2012-03-15
| | | | | | Patch by Richard Barton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152814 91177308-0d34-0410-b5e6-96231b3b80d8
* Split fpscr into two registers: FPSCR and FPSCR_NZCV.Lang Hames2012-03-06
| | | | | | | | | | | The fpscr register contains both flags (set by FP operations/comparisons) and control bits. The control bits (FPSCR) should be reserved, since they're always available and needn't be defined before use. The flag bits (FPSCR_NZCV) should like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM vpush/vpop assembler mnemonics accept an optional size suffix.Jim Grosbach2012-03-05
| | | | | | rdar://10988114 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152068 91177308-0d34-0410-b5e6-96231b3b80d8
* updated patch for the ARM fused multiply add/subSebastian Pop2012-03-05
| | | | | | | | | | | In this update: - I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2. - I kept setting .fpu=neon-vfpv4 code attribute because that is what the assembler understands. Patch by Ana Pazos <apazos@codeaurora.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152036 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-18
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Add fused multiple+add instructions from VFPv4.Anton Korobeynikov2012-01-22
| | | | | | | Patch by Ana Pazos! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148658 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-22
| | | | | | rdar://10558523 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some bogus comments.Jim Grosbach2011-12-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147169 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM pre-UAL aliases. fcmp[sd].Jim Grosbach2011-12-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147158 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VFP optional data type on VMOV GPR<-->SPR.Jim Grosbach2011-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VFP pre-UAL mnemonic aliases for fmul[sd].Jim Grosbach2011-12-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146892 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].Jim Grosbach2011-12-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146887 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON two-operand aliases for VQDMULH.Jim Grosbach2011-12-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.Jim Grosbach2011-12-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146508 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM add more 'gas' compatibility aliases for NEON instructions.Jim Grosbach2011-12-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146507 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.Jim Grosbach2011-12-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146300 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM add some pre-UAL VFP mnemonics for convenience when porting old code.Jim Grosbach2011-12-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146296 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM convenience aliases for VSQRT.Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146201 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VFP support 'fmrs/fmsr' aliases for 'vldr'Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146116 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VFP support 'flds/fldd' aliases for 'vldr'Jim Grosbach2011-12-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146115 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM tidy up and remove no longer needed InstAlias definitions.Jim Grosbach2011-12-07
| | | | | | The TokenAlias handling of data type suffices renders these unnecessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146010 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VFP assembly parsing for VADD and VSUB two-operand forms.Jim Grosbach2011-11-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144710 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM size suffix on VFP single-precision 'vmov' is optional.Jim Grosbach2011-11-15
| | | | | | rdar://10435114 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144698 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.Jim Grosbach2011-11-15
| | | | | | Yet more of rdar://10435076. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach2011-11-15
| | | | | | rdar://10449856. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VLDR/VSTR instructions don't need a size suffix.Jim Grosbach2011-11-14
| | | | | | | Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing type suffix options for VLDR/VSTR.Jim Grosbach2011-11-14
| | | | | | rdar://10435076 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144575 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM optional size suffix for VLDR/VSTR syntax.Jim Grosbach2011-11-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VMOV immediate.Jim Grosbach2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VMRS/FMSTAT.Jim Grosbach2011-10-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.Jim Grosbach2011-09-30
| | | | | | | | | | | | | Encode the immediate into its 8-bit form as part of isel rather than later, which simplifies things for mapping the encoding bits, allows the removal of the custom disassembler decoding hook, makes the operand printer trivial, and prepares things more cleanly for handling these in the asm parser. rdar://10211428 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140834 91177308-0d34-0410-b5e6-96231b3b80d8
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