| Commit message (Expand) | Author | Age |
|---|
| ... | |
| * | Next round of tail call changes. Register used in a tail | Dale Johannesen | 2010-06-15 |
| * | Clean up 80 column violations. No functional change. | Jim Grosbach | 2010-06-02 |
| * | Give SubRegIndex names to all ARM subregisters. This will be required by | Jakob Stoklund Olesen | 2010-05-26 |
| * | Replace the SubRegSet tablegen class with a less error-prone mechanism. | Jakob Stoklund Olesen | 2010-05-26 |
| * | Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." | Jakob Stoklund Olesen | 2010-05-26 |
| * | Replace the SubRegSet tablegen class with a less error-prone mechanism. | Jakob Stoklund Olesen | 2010-05-26 |
| * | Remove NumberHack entirely. | Jakob Stoklund Olesen | 2010-05-25 |
| * | Switch SubRegSet to using symbolic SubRegIndices | Jakob Stoklund Olesen | 2010-05-24 |
| * | Lose the dummies | Jakob Stoklund Olesen | 2010-05-24 |
| * | Replace the tablegen RegisterClass field SubRegClassList with an alist-like data | Jakob Stoklund Olesen | 2010-05-24 |
| * | Fix a few places that depended on the numeric value of subreg indices. | Jakob Stoklund Olesen | 2010-05-24 |
| * | Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums | Jakob Stoklund Olesen | 2010-05-24 |
| * | Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE | Evan Cheng | 2010-05-14 |
| * | Added a QQQQ register file to model 4-consecutive Q registers. | Evan Cheng | 2010-05-14 |
| * | Add comment about the pseudo registers QQ, each of which is a pair of Q regis... | Evan Cheng | 2010-05-13 |
| * | Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coa... | Evan Cheng | 2010-05-06 |
| * | Revert r103156 since it was breaking the build bots. | Eric Christopher | 2010-05-06 |
| * | Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registe... | Evan Cheng | 2010-05-06 |
| * | Make it SP, LR, PC for GPR Register Class instead of LR, SP, PC. | Johnny Chen | 2010-01-25 |
| * | Fixed the order of GPR RegisterClass regs to be: ..., R10, R11, R12, ... | Johnny Chen | 2010-01-25 |
| * | Remove the JustSP single-register regclass. | Jakob Stoklund Olesen | 2010-01-13 |
| * | Add a SPR register class to the ARM target. | Jakob Stoklund Olesen | 2009-12-22 |
| * | Add QPR_8 as a superreg class of SPR_8 and DPR_8. | Evan Cheng | 2009-11-03 |
| * | Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this wo... | Anton Korobeynikov | 2009-11-02 |
| * | Restrict Thumb1 register allocation to low registers, even for instructions that | Jim Grosbach | 2009-10-24 |
| * | FIXME no longer applies. R12 and R3 are available for allocation | Jim Grosbach | 2009-10-23 |
| * | Enable allocation of R3 in Thumb1 | Jim Grosbach | 2009-10-19 |
| * | Fix merge problem | Anton Korobeynikov | 2009-09-13 |
| * | Define proper subreg sets for arm - this should fix bunch of subtle problems | Anton Korobeynikov | 2009-09-13 |
| * | Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to | Anton Korobeynikov | 2009-09-12 |
| * | Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and | Anton Korobeynikov | 2009-09-08 |
| * | When using NEON for single-precision FP, the NEON result must be placed in D0... | David Goodwin | 2009-08-05 |
| * | In thumb mode, r7 is used as frame register. This fixes pr4681. | Evan Cheng | 2009-08-04 |
| * | Add VFP3 D registers to the DPR register class. | Evan Cheng | 2009-07-29 |
| * | Fix a obvious copy-n-paste bug. | Evan Cheng | 2009-07-22 |
| * | Model fpscr to prevent fcmped / fcmpezs etc from being deleted. | Evan Cheng | 2009-07-20 |
| * | Fix an obvious copy-and-paste error. | Bob Wilson | 2009-07-14 |
| * | Revert 75309. | Bob Wilson | 2009-07-14 |
| * | Add superclasses of ARM Neon quad registers. The Q2PR class contains pairs of | Bob Wilson | 2009-07-10 |
| * | Add support for ARM's Advanced SIMD (NEON) instruction set. | Bob Wilson | 2009-06-22 |
| * | For Darwin on ARMv6 and newer, make register r9 available for use as a | Bob Wilson | 2009-06-22 |
| * | Remove UseThumbBacktraces. Just check if subtarget is darwin. | Evan Cheng | 2009-06-18 |
| * | The attached patches implement most of the ARM AAPCS-VFP hard float | Anton Korobeynikov | 2009-06-08 |
| * | Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order chan... | Evan Cheng | 2009-06-05 |
| * | PR2985 / <rdar://problem/6584986> | Jim Grosbach | 2009-04-07 |
| * | Rename MRegisterInfo to TargetRegisterInfo. | Dan Gohman | 2008-02-10 |
| * | Remove attribution from file headers, per discussion on llvmdev. | Chris Lattner | 2007-12-29 |
| * | Use TableGen to emit information for dwarf register numbers. | Anton Korobeynikov | 2007-11-11 |
| * | Added ARM::CPSR to represent ARM CPSR status register. | Evan Cheng | 2007-07-05 |
| * | Specify S registers as D registers' sub-registers. | Evan Cheng | 2007-04-20 |
