| Commit message (Expand) | Author | Age |
|---|
| ... | |
| * | Add missing scheduling itineraries for transfers between core registers and V... | Evan Cheng | 2010-10-21 |
| * | Limit load / store issues (at least until we have a true multi-issue aware sc... | Evan Cheng | 2010-10-13 |
| * | More ARM scheduling itinerary fixes. | Evan Cheng | 2010-10-11 |
| * | Proper VST scheduling itineraries. | Evan Cheng | 2010-10-11 |
| * | Add VLD4 scheduling itineraries. | Evan Cheng | 2010-10-09 |
| * | Finish vld3 and vld4. | Evan Cheng | 2010-10-09 |
| * | Correct some load / store instruction itinerary mistakes: | Evan Cheng | 2010-10-09 |
| * | Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vld... | Evan Cheng | 2010-10-07 |
| * | - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This | Evan Cheng | 2010-10-06 |
| * | Major changes to Cortex-A9 itinerary. | Evan Cheng | 2010-10-03 |
| * | Fix r115332: correctly model AGU / NEON mux. | Evan Cheng | 2010-10-01 |
| * | Add operand cycles for vldr / vstr. | Evan Cheng | 2010-10-01 |
| * | NEON scheduling info fix. vmov reg, reg are single cycle instructions. | Evan Cheng | 2010-10-01 |
| * | Per Cortex-A9 pipeline diagram. AGU (core load / store issue) and NEON/FP iss... | Evan Cheng | 2010-10-01 |
| * | ARM instruction itinerary fixes: | Evan Cheng | 2010-09-30 |
| * | Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP | Evan Cheng | 2010-09-29 |
| * | Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. | Evan Cheng | 2010-09-29 |
| * | Assign bitwise binary instructions different itinerary classes from ALU instr... | Evan Cheng | 2010-09-29 |
| * | Add support to model pipeline bypass / forwarding. | Evan Cheng | 2010-09-28 |
| * | Fix IIC_iEXTAr itinerary class of Cortex-A9. | Evan Cheng | 2010-09-25 |
| * | Remove a unused instruction itinerary class. | Evan Cheng | 2010-09-25 |
| * | Fix zero and sign extension instructions scheduling itineraries. | Evan Cheng | 2010-09-25 |
| * | More pseudo instruction scheduling itinerary fixes. | Evan Cheng | 2010-09-24 |
| * | Fix scheduling itinerary for pseudo mov immediate instructions which expand i... | Evan Cheng | 2010-09-24 |
| * | Fix LDM_RET schedule itinery. | Evan Cheng | 2010-09-08 |
| * | minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. N... | Jim Grosbach | 2010-06-28 |
| * | Some A9 load/store cleanups | Anton Korobeynikov | 2010-05-29 |
| * | Some rough approximations for load/stores on A9 | Anton Korobeynikov | 2010-05-29 |
| * | NEON/VFP stuff can be issued only via Pipe1 on A9 | Anton Korobeynikov | 2010-05-29 |
| * | Add some integer instruction itineraries for A9 | Anton Korobeynikov | 2010-05-29 |
| * | Make processor FUs unique for given itinerary. This extends the limit of 32 | Anton Korobeynikov | 2010-04-18 |
| * | Split A8/A9 itins - they already were too big. | Anton Korobeynikov | 2010-04-07 |
