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path: root/lib/Target/ARM/Disassembler
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* Make the EDis tables const.Benjamin Kramer2012-02-11
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-07
* Enable streaming of bitcodeDerek Schuff2012-02-06
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-20
* ARM NEON VTBL/VTBX assembly parsing and encoding.Jim Grosbach2011-12-15
* ARM NEON refactor VST2 w/ writeback instructions.Jim Grosbach2011-12-14
* ARM NEON VST2 assembly parsing and encoding.Jim Grosbach2011-12-14
* LLVMBuild: Remove trailing newline, which irked me.Daniel Dunbar2011-12-12
* ARM assembly parsing and encoding for VLD2 with writeback.Jim Grosbach2011-12-09
* Remove unused variableMatt Beaumont-Gay2011-11-30
* ARM parsing for VLD1 all lanes, with writeback.Jim Grosbach2011-11-30
* ARM assembly parsing and encoding for four-register VST1.Jim Grosbach2011-11-29
* ARM assembly parsing and encoding for three-register VST1.Jim Grosbach2011-11-29
* build/CMake: Finish removal of add_llvm_library_dependencies.Daniel Dunbar2011-11-29
* Fix a misplaced paren bug.Owen Anderson2011-11-15
* Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VM...Owen Anderson2011-11-15
* build: Attempt to rectify inconsistencies between CMake and LLVMBuild version...Daniel Dunbar2011-11-12
* Re-apply 144430, this time with the associated isel and disassmbler bits.Jim Grosbach2011-11-12
* Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.Benjamin Kramer2011-11-11
* build: Add initial cut at LLVMBuild.txt files.Daniel Dunbar2011-11-03
* The rules disallowing single-register reglist operands only apply to the POP ...Owen Anderson2011-11-02
* Register list operands are not allowed to contain only a single register. Al...Owen Anderson2011-11-02
* Fix disassembly of some VST1 instructions.Owen Anderson2011-11-01
* ARM VST1 w/ writeback assembly parsing and encoding.Jim Grosbach2011-10-31
* More not-crashing NEON disassembly updates for the vld refactoring.Owen Anderson2011-10-31
* Reapply r143202, with a manual decoding hook for SWP. This change inadvertan...Owen Anderson2011-10-28
* Add some NEON stores to the VLD decoding hook that were accidentally omitted ...Owen Anderson2011-10-27
* ARM assembly parsing and encoding for VLD1 with writeback.Jim Grosbach2011-10-25
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-24
* ARM refactor am6offset usage for VLD1.Jim Grosbach2011-10-24
* Fix a NEON disassembly case that was broken in the recent refactorings. As m...Owen Anderson2011-10-24
* Move various generated tables into read-only memory, fixing up const correctn...Benjamin Kramer2011-10-22
* Assembly parsing for 4-register sequential variant of VLD2.Jim Grosbach2011-10-21
* Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach2011-10-21
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-21
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-21
* ARM VLD parsing and encoding.Jim Grosbach2011-10-21
* Tidy up. Trailing whitespace.Jim Grosbach2011-10-20
* Removed set, but unused variables.Chad Rosier2011-10-17
* Fix a non-firing assert. Change:Richard Trieu2011-10-14
* Fix undefined shift. Patch by Ahmed Charles.Eli Friedman2011-10-13
* SETEND is not allowed in an IT block.Owen Anderson2011-10-13
* ARM addrmode5 represents the 'U' bit of the encoding backwards.Jim Grosbach2011-10-12
* Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach2011-10-12
* addrmode2 is gone from these, so no need for the reg0 operand.Jim Grosbach2011-10-12
* Fix the check for nested IT instructions in the disassembler. We need to per...Owen Anderson2011-10-06
* Adding back support for printing operands symbolically to ARM's new disassemblerKevin Enderby2011-10-04
* ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.Jim Grosbach2011-09-30
* ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson2011-09-26
* Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid t...Owen Anderson2011-09-23