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* ARM: Correct printing of pre-indexed operands.Quentin Colombet2013-04-12
| | | | | | | | | | | | | | According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179398 91177308-0d34-0410-b5e6-96231b3b80d8
* Make ARMAsmPrinter generate the correct alignment specifier syntax in ↵Kristof Beyls2013-02-22
| | | | | | | | | | | instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a option to the disassembler to print immediates as hex.Kevin Enderby2012-12-05
| | | | | | | | | | | | | | | | | | | | | | This is for the lldb team so most of but not all of the values are to be printed as hex with this option. Some small values like the scale in an X86 address were requested to printed in decimal without the leading 0x. There may be some tweaks need to places that may still be in decimal that they want in hex. Specially for arm. I made my best guess. Any tweaks from here should be simple. I also did the best I know now with help from the C++ gurus creating the cleanest formatImm() utility function and containing the changes. But if someone has a better idea to make something cleaner I'm all ears and game for changing the implementation. rdar://8109283 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169393 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-03
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao2012-11-16
| | | | | | | | | | | This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168207 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Better disassembly for pc-relative LDR.Jim Grosbach2012-10-30
| | | | | | | | | When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166991 91177308-0d34-0410-b5e6-96231b3b80d8
* Make branch heavy code for generating marked up disassembly simplerKevin Enderby2012-10-23
| | | | | | | | and easier to read by adding a couple helper functions. Suggestion by Chandler Carruth and seconded by Meador Inge! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166515 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for annotated disassembly output for X86 and arm.Kevin Enderby2012-10-22
| | | | | | | | | | | | Per the October 12, 2012 Proposal for annotated disassembly output sent out by Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc tool now has a -mdis option to produced the marked up disassembly and a couple of small example test cases have been added. rdar://11764962 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166445 91177308-0d34-0410-b5e6-96231b3b80d8
* ARMInstPrinter.cpp: Fix a warning in -Asserts. [-Wunused-variable]NAKAMURA Takumi2012-09-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164459 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace.NAKAMURA Takumi2012-09-22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164458 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix edge cases of ARM shift operands in arith instructions.Tim Northover2012-09-22
| | | | | | | | | As before with load instructions, oddities like "asr #32", "rrx" could be printed incorrectly. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164456 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the handling of edge cases in ARM shifted operands.Tim Northover2012-09-22
| | | | | | | | | This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ↵Jiangning Liu2012-08-02
| | | | | | index issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161159 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Define generic HINT instruction.Jim Grosbach2012-06-18
| | | | | | | | | | | The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/ a different immediate value in bits [7,0]. Define a generic HINT instruction and refactor NOP, WFI, WFI, SEV and YIELD to be assembly aliases of that. rdar://11600518 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158674 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,Kevin Enderby2012-06-15
| | | | | | | iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158560 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missingKevin Enderby2012-05-17
| | | | | | | | | | | the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate ↵Silviu Baranga2012-05-11
| | | | | | offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156608 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor IT handling not to store the bottom bit of the condition code in ↵Richard Barton2012-04-27
| | | | | | the mask operand in the MCInst. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155700 91177308-0d34-0410-b5e6-96231b3b80d8
* For ARM disassembly only print 32 unsigned bits for the address of branchKevin Enderby2012-04-13
| | | | | | | | targets so if the branch target has the high bit set it does not get printed as: beq 0xffffffff8008c404 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154685 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getOpcodeName from the various target InstPrinters into the superclass ↵Benjamin Kramer2012-04-02
| | | | | | | | MCInstPrinter. All implementations used the same code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove getInstructionName from MCInstPrinter implementations in favor of ↵Craig Topper2012-04-02
| | | | | | using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863 91177308-0d34-0410-b5e6-96231b3b80d8
* Make MCInstrInfo available to the MCInstPrinter. This will be used to remove ↵Craig Topper2012-04-02
| | | | | | getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153860 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach2012-03-06
| | | | | | Register pair, all lanes subscripting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-06
| | | | | | | Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Kill some dead code.Jim Grosbach2012-03-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152131 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach2012-03-05
| | | | | | Use the new composite physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-05
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
* Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach2012-03-05
| | | | | | | Used to allow context sensitive printing of super-register or sub-register references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152043 91177308-0d34-0410-b5e6-96231b3b80d8
* Change ARMInstPrinter::printPredicateOperand() so it will not abort if itKevin Enderby2012-03-01
| | | | | | | runs into the undefined 15 condition code value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151844 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles2012-02-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150918 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-18
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON VLD4(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON VLD3(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON VLD4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148762 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON VLD3(multiple 3-element structures) assembly parsing.Jim Grosbach2012-01-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-22
| | | | | | rdar://10558523 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.Jim Grosbach2011-12-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding support for LDRD(label).Jim Grosbach2011-12-19
| | | | | | rdar://9932658 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON VST2 assembly parsing and encoding.Jim Grosbach2011-12-14
| | | | | | | | Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
* LLVMBuild: Remove trailing newline, which irked me.Daniel Dunbar2011-12-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146409 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM parsing for VLD1 two register all lanes, no writeback.Jim Grosbach2011-11-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM parsing aliases for VLD1 single register all lanes.Jim Grosbach2011-11-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
* build/CMake: Finish removal of add_llvm_library_dependencies.Daniel Dunbar2011-11-29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145420 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify some uses of utohexstr.Benjamin Kramer2011-11-07
| | | | | | As a side effect hex is printed lowercase instead of uppercase now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
* build: Add initial cut at LLVMBuild.txt files.Daniel Dunbar2011-11-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143634 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the issue that r143552 was trying to address the _right_ way. ↵Owen Anderson2011-11-02
| | | | | | One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143557 91177308-0d34-0410-b5e6-96231b3b80d8
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
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