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path: root/lib/Target/ARM/README-Thumb.txt
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* Testing commit access to llvm. Remove two lines of whitespace from the ↵Gordon Keiser2013-03-28
| | | | | | Thumb README. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178256 91177308-0d34-0410-b5e6-96231b3b80d8
* Add another note taken from the gcc bugzilla.Nick Lewycky2011-01-12
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* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable allocation of R3 in Thumb1Jim Grosbach2009-10-19
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* Another TODO.Evan Cheng2009-07-25
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* Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub ↵Evan Cheng2009-07-20
| | | | | | fp, #c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76401 91177308-0d34-0410-b5e6-96231b3b80d8
* Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is ↵Evan Cheng2009-07-11
| | | | | | feasible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75360 91177308-0d34-0410-b5e6-96231b3b80d8
* Major changes to Thumb (not Thumb2). Many 16-bit instructions either ↵Evan Cheng2009-07-11
| | | | | | | | | modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
* More info about Thumb1 predication support.Evan Cheng2009-07-10
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* Another todo entry.Evan Cheng2009-07-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75192 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a Thumb readme entry.Evan Cheng2009-07-09
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* Whitespace cleanup. Test commit.Jim Grosbach2008-08-12
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* Fix memcpy lowering when addresses are 4-byte aligned but size is not ↵Evan Cheng2007-10-22
| | | | | | multiple of 4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43234 91177308-0d34-0410-b5e6-96231b3b80d8
* update this entry, now that Anton implemented shift/and lowering forChris Lattner2007-06-02
| | | | | | | | switches. There is one really easy isel thing here with tst we are not getting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37400 91177308-0d34-0410-b5e6-96231b3b80d8
* New entry.Evan Cheng2007-03-29
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* New entry.Evan Cheng2007-03-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35206 91177308-0d34-0410-b5e6-96231b3b80d8
* New entry.Evan Cheng2007-02-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34000 91177308-0d34-0410-b5e6-96231b3b80d8
* UpdateEvan Cheng2007-02-07
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* Spill / restore should avoid modifying the condition register.Evan Cheng2007-02-07
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* Add a note.Evan Cheng2007-02-01
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* Possible JT improvements.Evan Cheng2007-02-01
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* Add entry.Evan Cheng2007-01-31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33723 91177308-0d34-0410-b5e6-96231b3b80d8
* New entry.Evan Cheng2007-01-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33569 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM backend contribution from Apple.Evan Cheng2007-01-19
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
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