| Commit message (Expand) | Author | Age |
|---|
| ... | |
| * | Hexagon: Set isPredicatedNew flag on predicate new instructions. | Jyotsna Verma | 2013-04-12 |
| * | Hexagon: Set isPredicatedFlase flag for all the instructions with negated pre... | Jyotsna Verma | 2013-04-12 |
| * | Hexagon: Expand br_cc. | Jyotsna Verma | 2013-04-04 |
| * | Remove unused typedef. | Duncan Sands | 2013-04-01 |
| * | There is no longer any need to silence this compiler warning as the warning has | Duncan Sands | 2013-03-31 |
| * | Hexagon: Add emitFrameIndexDebugValue function to emit debug information. | Jyotsna Verma | 2013-03-29 |
| * | Hexagon: Disable DwarfUsesInlineInfoSection flag. | Jyotsna Verma | 2013-03-29 |
| * | Hexagon: Replace switch-case in isDotNewInst with TSFlags. | Jyotsna Verma | 2013-03-28 |
| * | Hexagon: Enable SupportDebugInfomation and DwarfInSection flags. | Jyotsna Verma | 2013-03-28 |
| * | Hexagon: Use multiclass for gp-relative instructions. | Jyotsna Verma | 2013-03-28 |
| * | Switch to LLVM support function abs64 to keep VS2008 happy. | Tim Northover | 2013-03-27 |
| * | Hexagon: Disable optimizations at O0. | Jyotsna Verma | 2013-03-27 |
| * | Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. | Jyotsna Verma | 2013-03-26 |
| * | Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/... | Jyotsna Verma | 2013-03-26 |
| * | Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and w... | Jyotsna Verma | 2013-03-22 |
| * | Hexagon: Removed asserts regarding alignment and offset. | Jyotsna Verma | 2013-03-14 |
| * | Cleanup #includes. | Jakub Staszak | 2013-03-10 |
| * | DAGCombiner: Use correct value type for checking legality of BR_CC v3 | Tom Stellard | 2013-03-08 |
| * | Hexagon: Add patterns for zero extended loads from i1->i64. | Jyotsna Verma | 2013-03-08 |
| * | Hexagon: Handle i8, i16 and i1 Var Args. | Jyotsna Verma | 2013-03-07 |
| * | Hexagon: Add support to lower block address. | Jyotsna Verma | 2013-03-07 |
| * | reverting patch 176508. | Jyotsna Verma | 2013-03-05 |
| * | Hexagon: Add support for lowering block address. | Jyotsna Verma | 2013-03-05 |
| * | Hexagon: Expand addc, adde, subc and sube. | Jyotsna Verma | 2013-03-05 |
| * | Hexagon: Use MO operand flags to mark constant extended instructions. | Jyotsna Verma | 2013-03-05 |
| * | Hexagon: Add encoding bits to the TFR64 instructions. | Jyotsna Verma | 2013-03-05 |
| * | Added FIXME for future Hexagon cleanup. | Andrew Trick | 2013-03-02 |
| * | Hexagon: Add constant extender support framework. | Jyotsna Verma | 2013-03-01 |
| * | Remove code copied from GenRegisterInfo.inc. | Andrew Trick | 2013-02-22 |
| * | Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo | Eli Bendersky | 2013-02-21 |
| * | Hexagon: Expand cttz, ctlz, and ctpop for now. | Anshuman Dasgupta | 2013-02-21 |
| * | Update TargetLowering ivars for name policy. | Jim Grosbach | 2013-02-20 |
| * | Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h. | Jyotsna Verma | 2013-02-20 |
| * | Hexagon: Sync TSFlags in MCTargetDesc/HexagonBaseInfo.h with | Jyotsna Verma | 2013-02-19 |
| * | Hexagon: Set appropriate TSFlags to the loads/stores with global address to | Jyotsna Verma | 2013-02-15 |
| * | Hexagon: Change insn class to support instruction encoding. | Jyotsna Verma | 2013-02-14 |
| * | Hexagon: Use multiclass for absolute addressing mode loads. | Jyotsna Verma | 2013-02-14 |
| * | Hexagon: add support for predicate-GPR copies. | Anshuman Dasgupta | 2013-02-13 |
| * | Hexagon: Use absolute addressing mode loads/stores for global+offset | Jyotsna Verma | 2013-02-13 |
| * | MIsched: HazardRecognizers are created for each DAG. Free them. | Andrew Trick | 2013-02-13 |
| * | Hexagon: Add support to generate predicated absolute addressing mode | Jyotsna Verma | 2013-02-12 |
| * | Extend Hexagon hardware loop generation to handle various additional cases: | Krzysztof Parzyszek | 2013-02-11 |
| * | Implement HexagonInstrInfo::analyzeCompare. | Krzysztof Parzyszek | 2013-02-11 |
| * | Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle | Jyotsna Verma | 2013-02-05 |
| * | Hexagon: Use multiclass for absolute addressing mode stores. | Jyotsna Verma | 2013-02-05 |
| * | Move MRI liveouts to Hexagon return instructions. | Jakob Stoklund Olesen | 2013-02-05 |
| * | Hexagon: Add V4 compare instructions. Enable relationship mapping | Jyotsna Verma | 2013-02-05 |
| * | Hexagon: Add V4 combine instructions and some more Def Pats for V2. | Jyotsna Verma | 2013-02-04 |
| * | Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats". | Jyotsna Verma | 2013-02-01 |
| * | Add appropriate TSFlags to the instructions that must be always extended. | Jyotsna Verma | 2013-02-01 |
