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* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-19
| | | | | | caching it. The TLI may change between functions. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE ↵David Blaikie2013-06-16
| | | | | | | | | | MachineInstrs Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-15
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-07
| | | | | | | the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183490 91177308-0d34-0410-b5e6-96231b3b80d8
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-06
| | | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-31
| | | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
* Order CALLSEQ_START and CALLSEQ_END nodes.Andrew Trick2013-05-29
| | | | | | | | | | | | Fixes PR16146: gdb.base__call-ar-st.exp fails after pre-RA-sched=source fixes. Patch by Xiaoyi Guo! This also fixes an unsupported dbg.value test case. Codegen was previously incorrect but the test was passing by luck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Typo fix.Jyotsna Verma2013-05-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182790 91177308-0d34-0410-b5e6-96231b3b80d8
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-25
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Make helper functions static.Benjamin Kramer2013-05-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182588 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: SelectionDAG should not use MVT::Other to check the legality of BR_CC.Jyotsna Verma2013-05-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182390 91177308-0d34-0410-b5e6-96231b3b80d8
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't cast away constness.Benjamin Kramer2013-05-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182086 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead calls to addFrameMove.Rafael Espindola2013-05-16
| | | | | | Without a PROLOG_LABEL present, the cfi instructions are never printed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182016 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Pass to replace tranfer/copy instructions into combine instructionJyotsna Verma2013-05-14
| | | | | | | | where possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181817 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add patterns to generate 'combine' instructions.Jyotsna Verma2013-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181805 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: ArePredicatesComplement should not restrict itself to TFRs.Jyotsna Verma2013-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181803 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Remove dead-code after unconditional return from addPreSched2.Jyotsna Verma2013-05-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181797 91177308-0d34-0410-b5e6-96231b3b80d8
* Suppress GCC compiler warnings in release builds about variables that are onlyDuncan Sands2013-05-13
| | | | | | | read in asserts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181689 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the MachineMove class.Rafael Espindola2013-05-13
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
* Change getFrameMoves to return a const reference.Rafael Espindola2013-05-11
| | | | | | | To add a frame now there is a dedicated addFrameMove which also takes care of constructing the move itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181657 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix unused variable error.Jyotsna Verma2013-05-10
| | | | | | | | | Earlier, this variable was used in an assert and was causing failure on darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181630 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore.Jyotsna Verma2013-05-10
| | | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181628 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.Jyotsna Verma2013-05-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181624 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused argument.Rafael Espindola2013-05-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused function.Rafael Espindola2013-05-10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181606 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions.Jyotsna Verma2013-05-09
| | | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181535 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use relation map for getMatchingCondBranchOpcode() and Jyotsna Verma2013-05-09
| | | | | | | | getInvertedPredicatedOpcode() functions instead of switch cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181530 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Fix Small Data support to handle -G 0 correctly.Jyotsna Verma2013-05-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181344 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverting r181331.Jyotsna Verma2013-05-07
| | | | | | | | Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181334 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Fix Small Data support to handle -G 0 correctly.Jyotsna Verma2013-05-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181331 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Set accessSize and addrMode on all load/store instructions.Jyotsna Verma2013-05-07
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181324 91177308-0d34-0410-b5e6-96231b3b80d8
* Print IR from Hexagon MI passes with -print-before/after-all.Krzysztof Parzyszek2013-05-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181255 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup of the HexagonTargetMachine setup.Krzysztof Parzyszek2013-05-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181250 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.Jyotsna Verma2013-05-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181235 91177308-0d34-0410-b5e6-96231b3b80d8
* Make references to HexagonTargetMachine "const".Krzysztof Parzyszek2013-05-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181233 91177308-0d34-0410-b5e6-96231b3b80d8
* Use consistent function names.Krzysztof Parzyszek2013-05-04
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181090 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix missing include in Hexagon code for Release+AssertsReid Kleckner2013-05-03
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180983 91177308-0d34-0410-b5e6-96231b3b80d8
* reverting r180953Jyotsna Verma2013-05-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180964 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.Jyotsna Verma2013-05-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180953 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon - Add peephole optimizations for zero extends.Pranav Bhandarkar2013-05-02
| | | | | | | | | | | | | | * lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a sequence of a pair of i32->i64 extensions followed by a "bitwise or" into COMBINE_rr. * lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg. * test/CodeGen/Hexagon/union-1.ll: New test. * test/CodeGen/Hexagon/combine_ir.ll: Fix test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Honor __builtin_expect by using branch probabilities.Jyotsna Verma2013-05-02
| | | | | | | | | | | | | | | * lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp): Given a jump opcode return the right pred.new jump opcode with a taken vs not-taken hint based on branch probabilities provided by the target independent module. * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function. * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode): Enhance existing function use branch probabilities like HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180923 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use multiclass for Jump instructions.Jyotsna Verma2013-05-01
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180885 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Clear isKill flag on the predicate register inJyotsna Verma2013-05-01
| | | | | | | | PredicateInstruction function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180884 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.Jyotsna Verma2013-04-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180145 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Define relations for GP-relative instructions.Jyotsna Verma2013-04-23
| | | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180144 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Remove assembler mapped instruction definitions.Jyotsna Verma2013-04-23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180133 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Remove duplicate instructions to handle global/immediate valuesJyotsna Verma2013-04-23
| | | | | | | | for absolute/absolute-set addressing modes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180120 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.Tim Northover2013-04-20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
* ArrayRefize getMachineNode(). No functionality change.Michael Liao2013-04-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
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