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path: root/lib/Target/Mips/MipsDSPInstrInfo.td
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* [mips] Define a pseudo instruction which writes to both the lower and higherAkira Hatanaka2013-10-15
| | | | | | | | parts of the accumulators and gets expanded post-RA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192667 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use predicates to guard instructions using accumulator registers insteadAkira Hatanaka2013-10-15
| | | | | | | | of relying on AddedComplexity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192665 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename isel nodes.Akira Hatanaka2013-10-15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192663 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix definition of mfhi and mflo instructions to read from the wholeAkira Hatanaka2013-10-07
| | | | | | | | | | | | | | | | | accumulator instead of its sub-registers, $hi and $lo. We need this change to prevent a mflo following a mtlo from reading an unpredictable/undefined value, as shown in the following example: mult $6, $7 // result of $6 * $7 is written to $lo and $hi. mflo $2 // read lower 32-bit result from $lo. mtlo $4 // write to $lo. the content of $hi becomes unpredictable. mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value. I don't have a test case for this change that reliably reproduces the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fitAkira Hatanaka2013-09-07
| | | | | | | | into a 5-bit or 6-bit field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190226 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use ptr_rc to simplify definitions of base+index load/store instructions.Akira Hatanaka2013-08-28
| | | | | | | | Also, fix predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Resolve register classes dynamically using ptr_rc to reduce the number ofAkira Hatanaka2013-08-20
| | | | | | | | | | load/store instructions defined. Previously, we were defining load/store instructions for each pointer size (32 and 64-bit), but now we need just one definition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use register operands instead of register classes in DSP instructionAkira Hatanaka2013-08-14
| | | | | | | | definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188343 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename DSPRegs.Akira Hatanaka2013-08-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188342 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename HIRegs and LORegs.Akira Hatanaka2013-08-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename accumulator register classes and FP register operands.Akira Hatanaka2013-08-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Mark pseudo instructions as code-gen only.Akira Hatanaka2013-08-08
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188017 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-06
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Replace usages of register classes with register operands. Also, removeAkira Hatanaka2013-08-06
| | | | | | | | unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print jalr InstAliases in MipsInstPrinter::printAlias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Split the DSP control register and define one register for each field ofAkira Hatanaka2013-05-03
| | | | | | | | | | | | | its fields. This removes false dependencies between DSP instructions which access different fields of the the control register. Implicit register operands are added to instructions RDDSP and WRDSP after instruction selection, depending on the value of the mask operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Handle reading, writing or copying of ccond field of DSP controlAkira Hatanaka2013-05-02
| | | | | | | | | | | | | register. - Define pseudo instructions which store or load ccond field of the DSP control register. - Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack. - Expand the pseudos before callee-scan save. - Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180969 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix handling of instructions which copy to/from accumulator registers.Akira Hatanaka2013-04-30
| | | | | | | | | | | Expand copy instructions between two accumulator registers before callee-saved scan is done. Handle copies between integer GPR and hi/lo registers in MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Instruction selection patterns for DSP-ASE vector select and compareAkira Hatanaka2013-04-30
| | | | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180820 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Clear isCommutable bit of instructions which are not commutable.Akira Hatanaka2013-04-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180801 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] In performDSPShiftCombine, check that all elements in the vector areAkira Hatanaka2013-04-22
| | | | | | | | | shifted by the same amount and the shift amount is smaller than the element size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180039 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Instruction selection patterns for DSP-ASE vector shifts.Akira Hatanaka2013-04-19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179906 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] DSP-ASE move from HI/LO register instructions.Akira Hatanaka2013-04-18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179739 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Reapply r179420 and r179421.Akira Hatanaka2013-04-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179434 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r179420 and r179421.Akira Hatanaka2013-04-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179422 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Instruction selection patterns for carry-setting and using addAkira Hatanaka2013-04-12
| | | | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179421 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] v4i8 and v2i16 add, sub and mul instruction selection patterns.Akira Hatanaka2013-04-12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179420 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add patterns for DSP indexed load instructions.Akira Hatanaka2013-03-30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178408 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix DSP instructions to have explicit accumulator register operands.Akira Hatanaka2013-03-30
| | | | | | | | Check that instruction selection can select multiply-add/sub DSP instructions from a pattern that doesn't have intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Define pseudo instructions for spilling and copying accumulatorAkira Hatanaka2013-03-30
| | | | | | | registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178390 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass Akira Hatanaka2012-12-20
| | | | | | | parameter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170661 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Move class IsCommutable into MipsInstrInfo.td.Akira Hatanaka2012-12-13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170054 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: other miscellaneous instructions.Akira Hatanaka2012-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164845 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: ADDUH.QB instruction sub-class.Akira Hatanaka2012-09-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164840 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: ABSQ_S.PH instruction sub-class.Akira Hatanaka2012-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164787 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: SHLL.QB instruction sub-class.Akira Hatanaka2012-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164786 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: rddsp (instruction which reads DSPControl register fields to a GPR).Akira Hatanaka2012-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164756 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: CMPU.EQ.QB instruction sub-class.Akira Hatanaka2012-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164755 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: ADDU.QB instruction sub-class.Akira Hatanaka2012-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164754 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos ↵Akira Hatanaka2012-09-27
| | | | | | Field instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164751 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: all the remaining instructions which read or write accumulators.Akira Hatanaka2012-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164750 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: add support for extract-word instructions.Akira Hatanaka2012-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164749 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: add bitcast patterns between vectors and int.Akira Hatanaka2012-09-27
| | | | | | | No test cases. These patterns will get tested along with dsp intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164746 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: add vector load/store patterns.Akira Hatanaka2012-09-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164744 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: Add immediate leaves.Akira Hatanaka2012-09-22
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164435 91177308-0d34-0410-b5e6-96231b3b80d8
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