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path: root/lib/Target/Mips/MipsISelDAGToDAG.cpp
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* [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. ↵Daniel Sanders2013-11-12
| | | | | | not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194471 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. ↵Daniel Sanders2013-10-30
| | | | | | | | | | | | | | | | | | | not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching splati from normal IR (i.e. not ↵Daniel Sanders2013-09-27
| | | | | | | | | | intrinsics) Updated some of the vshf since they (correctly) emit splati's now git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191511 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching ↵Daniel Sanders2013-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191299 91177308-0d34-0410-b5e6-96231b3b80d8
* ISelDAG: spot chain cycles involving MachineNodesTim Northover2013-09-22
| | | | | | | | | | | | | | | | | Previously, the DAGISel function WalkChainUsers was spotting that it had entered already-selected territory by whether a node was a MachineNode (amongst other things). Since it's fairly common practice to insert MachineNodes during ISelLowering, this was not the correct check. Looking around, it seems that other nodes get their NodeId set to -1 upon selection, so this makes sure the same thing happens to all MachineNodes and uses that characteristic to determine whether we should stop looking for a loop during selection. This should fix PR15840. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191165 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added load/store intrinsics.Daniel Sanders2013-08-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189476 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips] Support for unaligned load/store microMips instructionsJack Carter2013-08-13
| | | | | | | | | This includes instructions lwl, lwr, swl and swr. Patch by Zoran Jovnovic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188312 91177308-0d34-0410-b5e6-96231b3b80d8
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-19
| | | | | | caching it. The TLI may change between functions. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-06
| | | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp.Akira Hatanaka2013-04-11
| | | | | | | | | | | - Rename function. - Pass iterator by value. - Remove header include. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179312 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some unused variables to clean the Clang -Werror buildDavid Blaikie2013-03-14
| | | | | | (these were added in r177089) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177129 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename functions and variables to start with proper case.Akira Hatanaka2013-03-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177092 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Define two subclasses of MipsDAGToDAGISel. Mips16DAGToDAGISel is forAkira Hatanaka2013-03-14
| | | | | | | | | | mips16 and MipsSEDAGToDAGISel is for mips32/64. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177089 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix inefficient code generation.Akira Hatanaka2013-03-01
| | | | | | | | | | | | | | | This patch eliminates the need to emit a constant move instruction when this pattern is matched: (select (setgt a, Constant), T, F) The pattern above effectively turns into this: (conditional-move (setlt a, Constant + 1), F, T) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176384 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Remove SDNPWantParent from the list of SDNodeProperties.Akira Hatanaka2013-02-16
| | | | | | | No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175325 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Split SelectAddr, which was used to match address patterns, into twoAkira Hatanaka2013-02-15
| | | | | | | | | | | | functions. Set AddedComplexity to determine the order in which patterns are matched. This simplifies selection of floating point loads/stores. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175300 91177308-0d34-0410-b5e6-96231b3b80d8
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-02
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-03
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add predicate HasFPIdx for floating-point indexed load instructionAkira Hatanaka2012-11-15
| | | | | | | | support and use it in place of HasMips32r2Or64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168089 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch is for the implementation of mips16 complex pattern addr16.Reed Kotler2012-10-28
| | | | | | | | | | | | | | | | | | | | | | | Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement carry for subtract/add for mips16Reed Kotler2012-10-26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166755 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch for integer multiply, signed/unsigned, long/long long.Reed Kotler2012-10-05
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165322 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td andAkira Hatanaka2012-09-15
| | | | | | | | | | | | use load/store fragments defined in TargetSelectionDAG.td in place of them. Unaligned loads/stores are either expanded or lowered to target-specific nodes, so instruction selection should see only aligned load/store nodes. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163960 91177308-0d34-0410-b5e6-96231b3b80d8
* In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if itsAkira Hatanaka2012-08-24
| | | | | | | | second operand is MipsISD::GPRel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162584 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't modify MO while use_iterator is still pointing to it.Jakob Stoklund Olesen2012-08-09
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161626 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined asAkira Hatanaka2012-07-31
| | | | | | | | | | | single-precision load and store. Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect to map unaligned floating point load/store nodes to these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161063 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate the stack slot used to save the global base register.Akira Hatanaka2012-07-25
| | | | | | | | | | The long branch pass (fixed in r160601) no longer uses the global base register to compute addresses of branch destinations, so it is not necessary to reserve a slot on the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160703 91177308-0d34-0410-b5e6-96231b3b80d8
* Add basic ability to setup call frame, and make procedure calls.Akira Hatanaka2012-07-23
| | | | | | | | | | Hello world will compile and execute with this patch. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160651 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert accidental commit.Akira Hatanaka2012-07-21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160598 91177308-0d34-0410-b5e6-96231b3b80d8
* Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.Akira Hatanaka2012-07-21
| | | | | | | Test case will be added later when long branch patch is checked in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160597 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence uninitialized variable warning in MipsISelDAGToDAG.cpp.Akira Hatanaka2012-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159243 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in computation of stack size in MipsFrameLowering.cpp.Akira Hatanaka2012-06-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159240 91177308-0d34-0410-b5e6-96231b3b80d8
* 1. fix null program output after some other changesAkira Hatanaka2012-06-21
| | | | | | | | | | 2. re-enable null.ll test 3. fix some minor style violations Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158935 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix coding style violations. Remove white spaces and tabs.Akira Hatanaka2012-06-14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158471 91177308-0d34-0410-b5e6-96231b3b80d8
* In MipsISelDAGToDAG.cpp, store the global base register to a stack frame object.Akira Hatanaka2012-06-14
| | | | | | | | Long-branches need access to the global base register to get the destination address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158428 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement a DAGCombine in MipsISelLowering.cpp which transforms the followingAkira Hatanaka2012-06-13
| | | | | | | | | | | pattern: (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) "tjt" is a TargetJumpTable node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158419 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer2012-06-02
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8
* Insert instructions to the entry basic block which initializes the globalAkira Hatanaka2012-05-12
| | | | | | | | | | | | | | | | | | | | pointer register. This is the first of the series of patches which clean up the way global pointer register is used. The patches will make the following improvements: - Make $gp an allocatable temporary register rather than reserving it. - Use a virtual register as the global pointer register and let the register allocator decide which register to assign to it or whether spill/reloads are needed. - Make sure $gp is valid at the entry of a called function, which is necessary for functions using lazy binding. - Remove the need for emitting .cprestore and .cpload directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156671 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not replace operands of pseudo instructions with register $zero.Akira Hatanaka2012-05-11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156663 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-20
| | | | | | since they are equivalent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
* Add T9 to the list of live-in registers of the entry basic block. Akira Hatanaka2012-03-27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153497 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch eliminates redundant instructions that produce 0.Akira Hatanaka2012-03-08
| | | | | | | | | | | | | | For example, the first instruction in the code below can be eliminated if the use of $vr0 is replaced with $zero: addiu $vr0, $zero, 0 add $vr2, $vr1, $vr0 add $vr2, $vr1, $zero git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152280 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bugs which were introduced when support for base+index floating point loadsAkira Hatanaka2012-03-01
| | | | | | | | | | | | | and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151843 91177308-0d34-0410-b5e6-96231b3b80d8
* remove blanks, and some code formatJia Liu2012-02-28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not reserve $gp as a dedicated global base register if the target ABI is ↵Akira Hatanaka2012-02-28
| | | | | | not O32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151614 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for floating point base register + offset register addressing modeAkira Hatanaka2012-02-28
| | | | | | | | load and store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151611 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an option to use a virtual register as the global base register instead ofAkira Hatanaka2012-02-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151402 91177308-0d34-0410-b5e6-96231b3b80d8
* remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.Jia Liu2012-02-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150805 91177308-0d34-0410-b5e6-96231b3b80d8
* add Emacs tag and fix some comment error in file headersJia Liu2012-02-17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150775 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. Akira Hatanaka2012-01-25
| | | | | | | | Add a test case to show fewer instructions are needed to load an immediate with the new way of loading immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148908 91177308-0d34-0410-b5e6-96231b3b80d8
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